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[34.150.132.193]) by smtp.gmail.com with ESMTPSA id q2-20020ac84502000000b00423829b6d91sm4242296qtn.8.2023.11.27.19.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 19:47:27 -0800 (PST) Date: Tue, 28 Nov 2023 03:47:26 +0000 From: Paz Zcharya To: Andrzej Hajda Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Fix phys_base to be relative not absolute Message-ID: References: <20231105172718.18673-1-pazz@chromium.org> <8dd6f4da-dcc9-4ea3-8395-bf048b0dbc93@intel.com> <6f08cfee-a60b-4f6e-b69a-20517c563259@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <6f08cfee-a60b-4f6e-b69a-20517c563259@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Subrata Banik , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, Marcin Wojtas , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Sean Paul , matthew.auld@intel.com, Rodrigo Vivi , Drew Davenport , Nirmoy Das Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, Nov 27, 2023 at 8:20 PM Paz Zcharya wrote: > > On 21.11.2023 13:06, Andrzej Hajda wrote: > > On 18.11.2023 00:01, Paz Zcharya wrote: > > > On Tue, Nov 14, 2023 at 10:13:59PM -0500, Rodrigo Vivi wrote: > > > > On Sun, Nov 05, 2023 at 05:27:03PM +0000, Paz Zcharya wrote: > > > > > > Hi Rodrigo, thanks for the great comments. > > > > > > Apologies for using a wrong/confusing terminology. I think 'phys_base' > > > is supposed to be the offset in the GEM BO, where base (or > > > "Surface Base Address") is supposed to be the GTT offset. > > > > Since base is taken from PLANE_SURF register it should be resolvable via > > GGTT to physical address pointing to actual framebuffer. > > I couldn't find anything in the specs. > > It was quite cryptic. I meant I have not found anything about assumption > from commit history that for iGPU there should be 1:1 mapping, this is why > there was an assignment "phys_base = base". Possibly the assumption is not > valid anymore for MTL(?). > Without the assumption we need to check GGTT to determine phys address. > > > The simplest approach would be then do the same as in case of DGFX: > > gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm; > > gen8_pte_t pte; > > > > gte += base / I915_GTT_PAGE_SIZE; > > > > pte = ioread64(gte); > > phys_base = pte & I915_GTT_PAGE_MASK; > > > > Regards > > Andrzej Hey Andrzej, On a second thought, what do you think about something like + gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm; + gen8_pte_t pte; + gte += base / I915_GTT_PAGE_SIZE; + pte = ioread64(gte); + pte = pte & I915_GTT_PAGE_MASK; + phys_base = pte - i915->mm.stolen_region->region.start; The only difference is the last line. Based on what I wrote before, I think `phys_base` is named incorrectly and that it does not reflect the physical address, but the start offset of i915->mm.stolen_region. So if we offset the start value of the stolen region, this code looks correct to me (and it also works on my MeteorLake device). What do you think? Many thanks, Paz