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[87.19.160.215]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c2997507sm168172766b.204.2024.09.27.13.15.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Sep 2024 13:15:24 -0700 (PDT) Message-ID: Date: Fri, 27 Sep 2024 22:15:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 05/11] drm/msm/a6xx: Implement preemption for a7xx targets To: Rob Clark Cc: Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Akhil P Oommen , Neil Armstrong , Sharat Masetty References: <20240926-preemption-a750-t-v6-0-7b6e1ef3648f@gmail.com> <20240926-preemption-a750-t-v6-5-7b6e1ef3648f@gmail.com> Content-Language: en-US From: Antonino Maniscalco In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 9/27/24 6:29 PM, Rob Clark wrote: > On Thu, Sep 26, 2024 at 2:17 PM Antonino Maniscalco > wrote: >> >> This patch implements preemption feature for A6xx targets, this allows >> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX >> hardware as such supports multiple levels of preemption granularities, >> ranging from coarse grained(ringbuffer level) to a more fine grained >> such as draw-call level or a bin boundary level preemption. This patch >> enables the basic preemption level, with more fine grained preemption >> support to follow. >> >> Reviewed-by: Akhil P Oommen >> Tested-by: Neil Armstrong # on SM8650-QRD >> Tested-by: Neil Armstrong # on SM8550-QRD >> Tested-by: Neil Armstrong # on SM8450-HDK >> Signed-off-by: Sharat Masetty >> Signed-off-by: Antonino Maniscalco >> --- >> drivers/gpu/drm/msm/Makefile | 1 + >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 283 +++++++++++++++++++++- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 168 +++++++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 377 ++++++++++++++++++++++++++++++ >> drivers/gpu/drm/msm/msm_ringbuffer.h | 7 + >> 5 files changed, 825 insertions(+), 11 deletions(-) >> > > [snip] > >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 6e065500b64d6d95599d89c33e6703c92f210047..355a3e210335d60a5bed0ee287912271c353402a 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > [snip] > >> @@ -784,6 +1015,16 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) >> msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); >> } >> >> + a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE, >> + MSM_BO_WC | MSM_BO_MAP_PRIV, >> + gpu->aspace, &a6xx_gpu->pwrup_reglist_bo, >> + &a6xx_gpu->pwrup_reglist_iova); > > Couldn't this also be MSM_BO_GPU_READONLY? And same for the > preempt_postamble_ptr, I assume? So for pwrup_reglist_ptr, it contains the cpu_gpu_lock struct that needs to be written by the gpu. The list itself is part of that struct. > > Also, it looks like we are only writing the smmu_info from the > kernel.. is there any way that could be split out into a RO buffer? For preempt_postamble_ptr, and smmu_info I think it should be possible so I'll work on that. > > BR, > -R > >> + >> + if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr)) >> + return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr); >> + >> + msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist"); >> + >> return 0; >> } >> Best regards, -- Antonino Maniscalco