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From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Tiago Martins Araújo" <tiago.martins.araujo@gmail.com>
Cc: Dave Airlie <airlied@gmail.com>,
	dri-devel@lists.freedesktop.org, simona@ffwll.ch,
	mpearson-lenovo@squebb.ca
Subject: Re: DisplayID checksum validation blocking hardware capabilities - CSO T3 panel
Date: Tue, 28 Oct 2025 21:08:10 +0200	[thread overview]
Message-ID: <a7d53f43e0c9d4c697946ecec31c9441df540a47@intel.com> (raw)
In-Reply-To: <CACRbrPHM=8DmTD2Wg__fBDpawuugA9C+CNr8-W8BJOnZfmobdA@mail.gmail.com>

On Mon, 15 Sep 2025, Tiago Martins Araújo <tiago.martins.araujo@gmail.com> wrote:
>> That's not the complete EDID data, though. It's missing 6*16 bytes. If
>> you go by the hex offsets, 0x100 does not follow 0x090.
>
>>  please grab the EDID from sysfs.
>
> Fresh from my terminal:
> ➜  ~ cat /sys/class/drm/card1-eDP-1/edid | edid-decode
> edid-decode (hex):
>
> 00 ff ff ff ff ff ff 00 0e 6f 16 14 00 00 00 00
> 00 20 01 04 b5 1e 13 78 03 21 15 a8 53 49 9c 25
> 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
> 01 01 01 01 01 01 ce 87 40 a0 b0 08 6a 70 30 20
> 36 00 2d bc 10 00 00 18 00 00 00 fd 00 28 78 e5
> e5 46 01 0a 20 20 20 20 20 20 00 00 00 fe 00 43
> 53 4f 54 20 54 33 0a 20 20 20 20 20 00 00 00 fe
> 00 4d 4e 45 30 30 37 5a 41 31 2d 35 0a 20 01 af
>
> 70 13 79 00 00 03 01 14 9a 0f 01 05 3f 0b 9f 00
> 2f 00 1f 00 07 07 69 00 02 00 05 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0 98
>
> ----------------
>
> Block 0, Base EDID:
>   EDID Structure Version & Revision: 1.4
>   Vendor & Product Identification:
>     Manufacturer: CSO
>     Model: 5142
>     Made in: 2022
>   Basic Display Parameters & Features:
>     Digital display
>     Bits per primary color channel: 10
>     DisplayPort interface
>     Maximum image size: 30 cm x 19 cm
>     Gamma: 2.20
>     Supported color formats: RGB 4:4:4
>     First detailed timing includes the native pixel format and preferred
> refresh rate
>     Display supports continuous frequencies
>   Color Characteristics:
>     Red  : 0.6562, 0.3261
>     Green: 0.2851, 0.6103
>     Blue : 0.1445, 0.0595
>     White: 0.3134, 0.3291
>   Established Timings I & II: none
>   Standard Timings: none
>   Detailed Timing Descriptors:
>     DTD 1:  2880x1800   60.000966 Hz  16:10   114.362 kHz    347.660000 MHz
> (301 mm x 188 mm)
>                  Hfront   48 Hsync  32 Hback   80 Hpol N
>                  Vfront    3 Vsync   6 Vback   97 Vpol N
>     Display Range Limits:
>       Monitor ranges (Range Limits Only): 40-120 Hz V, 229-229 kHz H, max
> dotclock 700 MHz
>     Alphanumeric Data String: 'CSOT T3'
>     Alphanumeric Data String: 'MNE007ZA1-5'
>   Extension blocks: 1
> Checksum: 0xaf
>
> ----------------
>
> Block 1, DisplayID Extension Block:
>   Version: 1.3
>   Extension Count: 0
>   Display Product Type: Extension Section
>   Video Timing Modes Type 1 - Detailed Timings Data Block:
>     DTD:  2880x1800  120.000207 Hz  16:10   228.720 kHz    695.310000 MHz
> (aspect 16:10, no 3D stereo)
>                Hfront   48 Hsync  32 Hback   80 Hpol N
>                Vfront    3 Vsync   6 Vback   97 Vpol N
>   Checksum: 0xf0 (should be 0xf8)
> Checksum: 0x98

There's an i915 bug report [1] on what is likely a similar Lenovo model
to yours, with the same display, but with an Intel GPU.

I looked at adding an EDID quirk for this, but actually passing the
information all the way down to the DisplayID checksum validation is
going to be annoying. :(


BR,
Jani.

[1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14703


-- 
Jani Nikula, Intel

  reply	other threads:[~2025-10-28 19:08 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-14 15:13 DisplayID checksum validation blocking hardware capabilities - CSO T3 panel Tiago Martins Araújo
2025-09-14 21:43 ` Dave Airlie
2025-09-15  9:24   ` Jani Nikula
2025-09-15 19:22     ` Tiago Martins Araújo
2025-10-28 19:08       ` Jani Nikula [this message]
2025-10-28 19:25         ` Tiago Martins Araújo
2025-10-28 20:09           ` Jani Nikula
2025-10-28 21:32             ` Tiago Martins Araújo
2025-10-30 10:51               ` Jani Nikula
2025-10-31 10:13               ` Jani Nikula
2025-10-31 10:42                 ` Tiago Martins Araújo
2025-09-15  8:51 ` Jani Nikula
2025-09-15  9:00   ` Jani Nikula

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