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From: Danilo Krummrich <dakr@kernel.org>
To: Alexandre Courbot <acourbot@nvidia.com>
Cc: "Miguel Ojeda" <ojeda@kernel.org>,
	"Alex Gaynor" <alex.gaynor@gmail.com>,
	"Boqun Feng" <boqun.feng@gmail.com>,
	"Gary Guo" <gary@garyguo.net>,
	"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
	"Andreas Hindborg" <a.hindborg@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"Trevor Gross" <tmgross@umich.edu>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Benno Lossin" <lossin@kernel.org>,
	"John Hubbard" <jhubbard@nvidia.com>,
	"Ben Skeggs" <bskeggs@nvidia.com>,
	"Joel Fernandes" <joelagnelf@nvidia.com>,
	"Timur Tabi" <ttabi@nvidia.com>,
	"Alistair Popple" <apopple@nvidia.com>,
	linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org,
	nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	"Lyude Paul" <lyude@redhat.com>
Subject: Re: [PATCH v5 15/23] gpu: nova-core: add falcon register definitions and base code
Date: Tue, 17 Jun 2025 18:33:13 +0200	[thread overview]
Message-ID: <aFGYyXS21tZFdldX@pollux> (raw)
In-Reply-To: <20250612-nova-frts-v5-15-14ba7eaf166b@nvidia.com>

On Thu, Jun 12, 2025 at 11:01:43PM +0900, Alexandre Courbot wrote:
> +    /// Perform a DMA write according to `load_offsets` from `dma_handle` into the falcon's
> +    /// `target_mem`.
> +    ///
> +    /// `sec` is set if the loaded firmware is expected to run in secure mode.
> +    fn dma_wr(
> +        &self,
> +        bar: &Bar0,
> +        dma_handle: bindings::dma_addr_t,

I think we should pass &F from dma_load() rather than the raw handle.

<snip>

> +fn select_core_ga102<E: FalconEngine>(bar: &Bar0) -> Result {
> +    let bcr_ctrl = regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE);
> +    if bcr_ctrl.core_select() != PeregrineCoreSelect::Falcon {
> +        regs::NV_PRISCV_RISCV_BCR_CTRL::default()
> +            .set_core_select(PeregrineCoreSelect::Falcon)
> +            .write(bar, E::BASE);
> +
> +        util::wait_on(Duration::from_millis(10), || {

As agreed, can you please add a brief comment to justify the timeout?

> +            let r = regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE);
> +            if r.valid() {
> +                Some(())
> +            } else {
> +                None
> +            }
> +        })?;
> +    }
> +
> +    Ok(())
> +}
> +
> +fn signature_reg_fuse_version_ga102(
> +    dev: &device::Device,
> +    bar: &Bar0,
> +    engine_id_mask: u16,
> +    ucode_id: u8,
> +) -> Result<u32> {
> +    // The ucode fuse versions are contained in the FUSE_OPT_FPF_<ENGINE>_UCODE<X>_VERSION
> +    // registers, which are an array. Our register definition macros do not allow us to manage them
> +    // properly, so we need to hardcode their addresses for now.

Sounds like a TODO?

> +
> +    // Each engine has 16 ucode version registers numbered from 1 to 16.
> +    if ucode_id == 0 || ucode_id > 16 {
> +        dev_err!(dev, "invalid ucode id {:#x}", ucode_id);
> +        return Err(EINVAL);
> +    }
> +
> +    // Base address of the FUSE registers array corresponding to the engine.
> +    let reg_fuse_base = if engine_id_mask & 0x0001 != 0 {
> +        regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::OFFSET
> +    } else if engine_id_mask & 0x0004 != 0 {
> +        regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::OFFSET
> +    } else if engine_id_mask & 0x0400 != 0 {
> +        regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::OFFSET
> +    } else {
> +        dev_err!(dev, "unexpected engine_id_mask {:#x}", engine_id_mask);
> +        return Err(EINVAL);
> +    };
> +
> +    // Read `reg_fuse_base[ucode_id - 1]`.
> +    let reg_fuse_version =
> +        bar.read32(reg_fuse_base + ((ucode_id - 1) as usize * core::mem::size_of::<u32>()));
> +
> +    Ok(fls_u32(reg_fuse_version))
> +}
> +
> +fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) -> Result {
> +    regs::NV_PFALCON2_FALCON_BROM_PARAADDR::default()
> +        .set_value(params.pkc_data_offset)
> +        .write(bar, E::BASE);
> +    regs::NV_PFALCON2_FALCON_BROM_ENGIDMASK::default()
> +        .set_value(params.engine_id_mask as u32)
> +        .write(bar, E::BASE);
> +    regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::default()
> +        .set_ucode_id(params.ucode_id)
> +        .write(bar, E::BASE);
> +    regs::NV_PFALCON2_FALCON_MOD_SEL::default()
> +        .set_algo(FalconModSelAlgo::Rsa3k)
> +        .write(bar, E::BASE);
> +
> +    Ok(())
> +}
> +
> +pub(super) struct Ga102<E: FalconEngine>(PhantomData<E>);
> +
> +impl<E: FalconEngine> Ga102<E> {
> +    pub(super) fn new() -> Self {
> +        Self(PhantomData)
> +    }
> +}
> +
> +impl<E: FalconEngine> FalconHal<E> for Ga102<E> {
> +    fn select_core(&self, _falcon: &Falcon<E>, bar: &Bar0) -> Result {
> +        select_core_ga102::<E>(bar)
> +    }
> +
> +    fn signature_reg_fuse_version(
> +        &self,
> +        falcon: &Falcon<E>,
> +        bar: &Bar0,
> +        engine_id_mask: u16,
> +        ucode_id: u8,
> +    ) -> Result<u32> {
> +        signature_reg_fuse_version_ga102(&falcon.dev, bar, engine_id_mask, ucode_id)
> +    }
> +
> +    fn program_brom(&self, _falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) -> Result {
> +        program_brom_ga102::<E>(bar, params)
> +    }

Why are those two separate functions?

  reply	other threads:[~2025-06-17 16:33 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-12 14:01 [PATCH v5 00/23] nova-core: run FWSEC-FRTS to perform first stage of GSP initialization Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 01/23] rust: dma: expose the count and size of CoherentAllocation Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 02/23] rust: make ETIMEDOUT error available Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 03/23] rust: sizes: add constants up to SZ_2G Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 04/23] rust: add new `num` module with `PowerOfTwo` type Alexandre Courbot
2025-06-12 15:07   ` Boqun Feng
2025-06-12 20:00     ` John Hubbard
2025-06-12 20:05       ` Boqun Feng
2025-06-12 20:08         ` John Hubbard
2025-06-12 20:12           ` Boqun Feng
2025-06-13 14:16     ` Alexandre Courbot
2025-06-13 15:25       ` Boqun Feng
2025-06-14 17:08       ` Boqun Feng
2025-06-16  5:14         ` Alexandre Courbot
2025-06-14 17:31   ` Boqun Feng
2025-06-16  5:19     ` Alexandre Courbot
2025-06-14 19:09   ` Benno Lossin
2025-06-15 13:32   ` Miguel Ojeda
2025-06-16  5:13     ` Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 05/23] rust: num: add the `fls` operation Alexandre Courbot
2025-06-14 19:16   ` Benno Lossin
2025-06-16  6:41     ` Alexandre Courbot
2025-06-18 19:24       ` Benno Lossin
2025-06-19 13:26         ` Alexandre Courbot
2025-06-19 13:28           ` Benno Lossin
2025-06-15  9:37   ` Miguel Ojeda
2025-06-15 10:51     ` Alexandre Courbot
2025-06-15 10:58       ` Alexandre Courbot
2025-06-15 13:25         ` Miguel Ojeda
2025-06-16  6:36           ` Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 06/23] gpu: nova-core: use absolute paths in register!() macro Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 07/23] gpu: nova-core: add delimiter for helper rules " Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 08/23] gpu: nova-core: expose the offset of each register as a type constant Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 09/23] gpu: nova-core: allow register aliases Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 10/23] gpu: nova-core: increase BAR0 size to 16MB Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 11/23] gpu: nova-core: add helper function to wait on condition Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 12/23] gpu: nova-core: wait for GFW_BOOT completion Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 13/23] gpu: nova-core: add DMA object struct Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 14/23] gpu: nova-core: register sysmem flush page Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 15/23] gpu: nova-core: add falcon register definitions and base code Alexandre Courbot
2025-06-17 16:33   ` Danilo Krummrich [this message]
2025-06-18  5:26     ` Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 16/23] gpu: nova-core: firmware: add ucode descriptor used by FWSEC-FRTS Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 17/23] gpu: nova-core: vbios: Add base support for VBIOS construction and iteration Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 18/23] gpu: nova-core: vbios: Add support to look up PMU table in FWSEC Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 19/23] gpu: nova-core: vbios: Add support for FWSEC ucode extraction Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 20/23] gpu: nova-core: compute layout of the FRTS region Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 21/23] gpu: nova-core: add types for patching firmware binaries Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 22/23] gpu: nova-core: extract FWSEC from BIOS and patch it to run FWSEC-FRTS Alexandre Courbot
2025-06-12 14:01 ` [PATCH v5 23/23] gpu: nova-core: load and " Alexandre Courbot
2025-06-18 20:23   ` Danilo Krummrich
2025-06-18 20:24     ` Danilo Krummrich
2025-06-19 12:35       ` Alexandre Courbot
2025-06-19 12:43         ` Danilo Krummrich
2025-06-17 20:14 ` [PATCH v5 00/23] nova-core: run FWSEC-FRTS to perform first stage of GSP initialization Danilo Krummrich
2025-06-18  8:25   ` Alexandre Courbot
2025-06-18 20:14 ` Danilo Krummrich
2025-06-19  7:14   ` Alexandre Courbot

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