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[97.120.250.80]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3158a25617asm985583a91.33.2025.06.18.19.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 19:50:18 -0700 (PDT) Date: Wed, 18 Jun 2025 19:50:16 -0700 From: Drew Fustini To: Michal Wilczynski Cc: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v5 7/8] riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node Message-ID: References: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> <20250618-apr_14_for_sending-v5-7-27ed33ea5c6f@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250618-apr_14_for_sending-v5-7-27ed33ea5c6f@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Jun 18, 2025 at 12:22:13PM +0200, Michal Wilczynski wrote: > Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD > TH1520 SoC used by the Lichee Pi 4A board. This node enables support for > the GPU using the drm/imagination driver. > > By adding this node, the kernel can recognize and initialize the GPU, > providing graphics acceleration capabilities on the Lichee Pi 4A and > other boards based on the TH1520 SoC. > > Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be > controlled programatically. > > Reviewed-by: Ulf Hansson > Signed-off-by: Michal Wilczynski > --- > arch/riscv/boot/dts/thead/th1520.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > index f3f5db0201ab8c0306d4d63072a1573431e51893..c8447eef36c3a6e92d768658b6b19dfeb59a47c4 100644 > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -225,6 +225,13 @@ aonsys_clk: clock-73728000 { > #clock-cells = <0>; > }; > > + gpu_mem_clk: mem-clk { > + compatible = "fixed-clock"; > + clock-frequency = <0>; > + clock-output-names = "gpu_mem_clk"; > + #clock-cells = <0>; > + }; > + > stmmac_axi_config: stmmac-axi-config { > snps,wr_osr_lmt = <15>; > snps,rd_osr_lmt = <15>; > @@ -500,6 +507,21 @@ clk: clock-controller@ffef010000 { > #clock-cells = <1>; > }; > > + gpu: gpu@ffef400000 { > + compatible = "thead,th1520-gpu", "img,img-bxm-4-64", > + "img,img-rogue"; > + reg = <0xff 0xef400000 0x0 0x100000>; > + interrupt-parent = <&plic>; > + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk_vo CLK_GPU_CORE>, > + <&gpu_mem_clk>, > + <&clk_vo CLK_GPU_CFG_ACLK>; > + clock-names = "core", "mem", "sys"; > + power-domains = <&aon TH1520_GPU_PD>; > + power-domain-names = "a"; > + resets = <&rst TH1520_RESET_ID_GPU>; > + }; > + > rst: reset-controller@ffef528000 { > compatible = "thead,th1520-reset"; > reg = <0xff 0xef528000 0x0 0x4f>; > > -- > 2.34.1 > Reviewed-by: Drew Fustini