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[97.120.250.80]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-748fbce0f13sm291934b3a.37.2025.06.18.18.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 18:43:36 -0700 (PDT) Date: Wed, 18 Jun 2025 18:43:34 -0700 From: Drew Fustini To: Michal Wilczynski Cc: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Krzysztof Kozlowski Subject: Re: [PATCH v5 0/8] Add TH1520 GPU support with power sequencing Message-ID: References: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Jun 18, 2025 at 12:22:06PM +0200, Michal Wilczynski wrote: > This patch series introduces support for the Imagination IMG BXM-4-64 > GPU found on the T-HEAD TH1520 SoC. A key aspect of this support is > managing the GPU's complex power-up and power-down sequence, which > involves multiple clocks and resets. > > The TH1520 GPU requires a specific sequence to be followed for its > clocks and resets to ensure correct operation. Initial discussions and > an earlier version of this series explored managing this via the generic > power domain (genpd) framework. However, following further discussions > with kernel maintainers [1], the approach has been reworked to utilize > the dedicated power sequencing (pwrseq) framework. > > This revised series now employs a new pwrseq provider driver > (pwrseq-thead-gpu.c) specifically for the TH1520 GPU. This driver > encapsulates the SoC specific power sequence details. The Imagination > GPU driver (pvr_device.c) is updated to act as a consumer of this power > sequencer, requesting the "gpu-power" target. The sequencer driver, > during its match phase with the GPU device, acquires the necessary clock > and reset handles from the GPU device node to perform the full sequence. > > This approach aligns with the goal of abstracting SoC specific power > management details away from generic device drivers and leverages the > pwrseq framework as recommended. > > The series is structured as follows: > > Patch 1: Introduces the pwrseq-thead-gpu auxiliary driver to manage the > GPU's power-on/off sequence. > Patch 2: Adds device tree bindings for the gpu-clkgen reset to the > existing thead,th1520-aon binding. > Patch 3: Extends the pm-domains driver to detect the gpu-clkgen reset > and spawn the pwrseq-thead-gpu auxiliary driver. > Patch 4: Updates the Imagination DRM driver to utilize the pwrseq > framework for TH1520 GPU power management. > Patch 5: Adds the thead,th1520-gpu compatible string to the PowerVR GPU > device tree bindings. > Patch 6: Adds the gpu-clkgen reset property to the aon node in the > TH1520 device tree source. > Patch 7: Adds the device tree node for the IMG BXM-4-64 GPU and its > required fixed-clock. > Patch 8: Enables compilation of the Imagination PowerVR driver on the > RISC-V architecture. > > This patchset finishes the work started in bigger series [2] by adding > all remaining GPU power sequencing piece. After this patchset the GPU > probes correctly. The powevr probe complains: [ 1.060383] powervr ffef400000.gpu: Direct firmware load for powervr/rogue_36.52.104.182_v1.fw failed with error -2 Where is the correct place to get the firmware? Thanks, Drew