[PATCH 00/23] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[PATCH 00/23] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[Ankit Nautiyal]

Enable Adaptive Sync SDP for Panel replay + auxless ALPM.
First few patches are fixes in existing AS SDP enablement.
Later patches add the support to send AS SDP for Panel replay with Link
ON and with auxless ALPM (Link-Off). 

This series is in continuation from discussions in [1] [2] and more
recent [3]:

Apart from few patches from [3] new changes include:
- Some clean up in drm/dp Macros
- Add new DPCD bit to get FAVT PAYLOAD FIELDS PARSING SUPPORT.
- Add AS SDP version and PR and VRR specific bits in drm_dp.h.
- Modify AS SDP compute config to accomodate PR with Link On and Link
  Off.
- Program Downspread Ctrl DPCD bits.
- Make way for T1 and T2 AS SDP transmission timing/position.

[1] https://lore.kernel.org/all/1b8c6c6de1e5fe0db83e6ae942dfee7e6f950767.camel@intel.com/
[2] https://lore.kernel.org/all/aPtqdAxDwiuQZbrn@intel.com/
[3] https://lore.kernel.org/intel-gfx/7c2d6f4e-69e6-452a-89cc-5fd4254430bd@intel.com/T/#m6e8beab2cc3b6ff9d61f740f107d83a2f4e08114

Rev2:
 - Drop the redundant version member for AS SDP, and use the member
   revision
 - Drop member to store AS SDP transmission time, use simple helper
   instead.
 - Use Burst mode to write Panel Replay config DPCDs.
 - Split AS SDP configuration in compute_config() and
   compute_config_late() phase.
 - Always enable AS SDP whenever supported by source + sink.

Rev3:
 - Use ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit also to determine AS
   SDP v2 support.
 - Drop patch to make provision to send AS SDP v1.
 - Add patch to include all relevant AS SDP fields in comparison.
 - Other refactor improvements suggested by Ville.

Rev4:
 - Add new member coasting vtotal in struct drm_dp_as_sdp and program
   the coasting vtotal in AS SDP.
 - Add new helper to get async timing support during PR active.
 - Correct the patches to write Panel Replay Config DPCDs.
 - Ensure either PR/VRR have potential to use AS SDP before enabling
   AS SDP, even though we may not be enabling them at modeset.
 - Other correction and changes suggested by Ville.

Ankit Nautiyal (23):
  drm/dp: Rename and relocate AS SDP payload field masks
  drm/dp: Clean up DPRX feature enumeration macros
  drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support
  drm/dp: Add DPCD for configuring AS SDP for PR + VRR
  drm/dp: Store coasting vtotal in struct drm_dp_as_sdp
  drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP
  drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink
  drm/i915/dp: Account for AS_SDP guardband only when enabled
  drm/i915/dp: Add a helper to decide if AS SDP can be used
  drm/i915/dp: Skip AS SDP for DP branch devices
  drm/i915/dp: Use revision field of AS SDP data structure
  drm/i915/dp: Include all relevant AS SDP fields in comparison
  drm/i915/psr: Add helper to get Async Video timing support in PR
    active
  drm/i915/dp: Add member to intel_dp to store AS SDP v2 support
  drm/i915/dp: Allow AS SDP only if v2 is supported
  drm/i915/psr: Write the PR config DPCDs in burst mode
  drm/i915/display: Add helper for AS SDP transmission time selection
  drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission
    time
  drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless
    ALPM
  drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off
  drm/i915/dp: Split AS SDP computation between compute_config and
    compute_config_late
  drm/i915/dp: Compute and include coasting vtotal for AS SDP
  drm/i915/dp: Always enable AS SDP if supported by source + sink

 drivers/gpu/drm/display/drm_dp_helper.c       |   1 +
 drivers/gpu/drm/i915/display/intel_alpm.c     |  20 ++-
 drivers/gpu/drm/i915/display/intel_display.c  |   9 +-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 165 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +
 .../drm/i915/display/intel_dp_link_training.c |  12 +-
 .../drm/i915/display/intel_dp_link_training.h |   3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  37 ++--
 drivers/gpu/drm/i915/display/intel_psr.h      |   1 +
 drivers/gpu/drm/i915/display/intel_vrr.c      |  10 ++
 include/drm/display/drm_dp.h                  |  20 ++-
 include/drm/display/drm_dp_helper.h           |   1 +
 14 files changed, 226 insertions(+), 58 deletions(-)

-- 
2.45.2

[PATCH 01/23] drm/dp: Rename and relocate AS SDP payload field masks

[Ankit Nautiyal]

The AS SDP payload field masks were misnamed and placed under the DPRX
feature enumeration list. These are not DPRX capability bits, but are
payload field masks for the Adaptive Sync SDP.

Relocate both masks next to the AS SDP definitions.
Update users to the corrected names. No functional change.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
 include/drm/display/drm_dp.h            | 5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4955bd8b11d7..602efaf500bd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5295,8 +5295,8 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
-	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
-	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
+	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
+	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8b15d3eeb716..4ea3b5b08a12 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1204,8 +1204,6 @@
 
 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
-# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE		GENMASK(1, 0)
-# define DP_ADAPTIVE_SYNC_SDP_LENGTH				GENMASK(5, 0)
 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
 
@@ -1870,4 +1868,7 @@ enum operation_mode {
 	DP_AS_SDP_FAVT_TRR_REACHED = 0x03
 };
 
+#define DP_AS_SDP_OPERATION_MODE_MASK	GENMASK(1, 0)
+#define DP_AS_SDP_LENGTH_MASK		GENMASK(5, 0)
+
 #endif /* _DRM_DP_H_ */
-- 
2.45.2

[PATCH 02/23] drm/dp: Clean up DPRX feature enumeration macros

[Ankit Nautiyal]

Align the DP_DPRX feature enumeration macros for better readability and
consistency, and use the BIT() macro instead of open-coded shifts.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 include/drm/display/drm_dp.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 4ea3b5b08a12..49f0154eb93c 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1202,10 +1202,10 @@
 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS	0x04
 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS	0x05
 
-#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
-# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
-# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
-# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
+#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
+# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
+# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
+# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
 
 #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
 # define DP_UHBR10                             (1 << 0)
-- 
2.45.2

[PATCH 03/23] drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support

[Ankit Nautiyal]

DP v2.1 introduced support for sending AS SDP payload bytes for FAVT.
Add the relavant bits for the same.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 include/drm/display/drm_dp.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 49f0154eb93c..8d172863eba3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1205,6 +1205,7 @@
 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
+# define DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED			BIT(2) /* 2.1 */
 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
 
 #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
-- 
2.45.2

[PATCH 04/23] drm/dp: Add DPCD for configuring AS SDP for PR + VRR

[Ankit Nautiyal]

Add additional DPCDs required to be configured to support VRR with Panel
Replay. These DPCDs are specifically required for configuring Adaptive Sync
SDP and are introduced in DP v2.1.

v2:
 - Correct the shift for the bits. (Ville)
 - Add DP_PR_ prefix for the PR-related fields.
v3:
 - Use macro values in their shifted form to match the convention. (Ville)
v4:
 - Add macro for the mask. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8d172863eba3..829e4d98d61c 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -718,6 +718,12 @@
 #define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_GRANT	    0x119   /* 1.4a */
 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_GRANTED	    (1 << 0)
 
+#define PANEL_REPLAY_CONFIG3			0x11a /* DP 2.1 */
+# define DP_PR_AS_SDP_SETUP_TIME_MASK		(3 << 6)
+# define DP_PR_AS_SDP_SETUP_TIME_T1		(0 << 6)
+# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC	(1 << 6) /* DP 2.1 Table 2-227 */
+# define DP_PR_AS_SDP_SETUP_TIME_T2		(2 << 6)
+
 #define DP_FEC_CONFIGURATION		    0x120    /* 1.4 */
 # define DP_FEC_READY			    (1 << 0)
 # define DP_FEC_ERR_COUNT_SEL_MASK	    (7 << 1)
-- 
2.45.2

[PATCH 05/23] drm/dp: Store coasting vtotal in struct drm_dp_as_sdp

[Ankit Nautiyal]

Add new field in struct drm_dp_as_sdp to store coasting vtotal.
This is used by the sinks that support Panel Replay and Asynchronous
timing during PR Active to derive refresh rate, when AS SDP transmission
is stopped by the source.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 1 +
 include/drm/display/drm_dp_helper.h     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index a697cc227e28..e29958f8b0b6 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -3512,6 +3512,7 @@ void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp
 	drm_printf(p, "    duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
 	drm_printf(p, "    duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
 	drm_printf(p, "    operation_mode: %d\n", as_sdp->mode);
+	drm_printf(p, "    coasting vtotal: %d\n", as_sdp->coasting_vtotal);
 }
 EXPORT_SYMBOL(drm_dp_as_sdp_log);
 
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 1d0acd58f486..8c2d77a032f0 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -126,6 +126,7 @@ struct drm_dp_as_sdp {
 	int duration_decr_ms;
 	bool target_rr_divider;
 	enum operation_mode mode;
+	int coasting_vtotal;
 };
 
 void drm_dp_as_sdp_log(struct drm_printer *p,
-- 
2.45.2

[PATCH 06/23] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP

[Ankit Nautiyal]

Correct the bit-shift logic to properly readback the 10 bit target_rr from
DB3 and DB4.

v2: Align the style with readback for vtotal. (Ville)

Fixes: 12ea89291603 ("drm/i915/dp: Add Read/Write support for Adaptive Sync SDP")
Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 602efaf500bd..49eeb35973a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5298,7 +5298,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
 	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
-	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
 
 	return 0;
-- 
2.45.2

[PATCH 07/23] drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink

[Ankit Nautiyal]

Currently we do not support VRR with HDMI so skip vrr compute
config step for all DP branch devices.

v2: Restrict VRR on all DP branch devices instead for checking only for
    HDMI. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8a957804cb97..160e1c24aa4b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,6 +55,16 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 		if (connector->mst.dp)
 			return false;
 		intel_dp = intel_attached_dp(connector);
+		/*
+		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
+		 * via a PCON could support VRR. However, supporting VRR through a
+		 * PCON requires non-trivial changes that are not implemented yet.
+		 * Until that support exists, avoid VRR on all DP branch devices.
+		 *
+		 * TODO: Add support for VRR for DP->HDMI 2.1 PCON.
+		 */
+		if (drm_dp_is_branch(intel_dp->dpcd))
+			return false;
 
 		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
 			return false;
-- 
2.45.2

[PATCH 08/23] drm/i915/dp: Account for AS_SDP guardband only when enabled

[Ankit Nautiyal]

Currently the intel_dp_sdp_min_guardband() accounts for AS_SDP for all
platforms that support adaptive sync SDP even for configurations where
it cannot be enabled. Instead account for adaptive sync SDP guardband
only when it is enabled.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 49eeb35973a1..499850c2abcf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7374,7 +7374,6 @@ int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 ty
 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 			       bool assume_all_enabled)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
 	int sdp_guardband = 0;
 
 	if (assume_all_enabled ||
@@ -7389,8 +7388,8 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));
 
-	if ((assume_all_enabled && HAS_AS_SDP(display)) ||
-	    crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+	if (crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
 
-- 
2.45.2

[PATCH 09/23] drm/i915/dp: Add a helper to decide if AS SDP can be used

[Ankit Nautiyal]

Add a helper that determines whether AS SDP can be used for the
current DP configuration. For now this is true only when the sink
supports AS SDP and VRR is enabled, but more conditions may be added
later.

v2:
 - Rename to intel_dp_needs_as_sdp(). (Ville)
 - Add a #FIXME documenting non-atomic of DP SDP updates. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 499850c2abcf..3d0ea074e610 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3124,6 +3124,15 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
 }
 
+static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
+				  struct intel_crtc_state *crtc_state)
+{
+	if (!intel_dp->as_sdp_supported)
+		return false;
+
+	return crtc_state->vrr.enable;
+}
+
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -3131,7 +3140,12 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 
-	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
+	/*
+	 * #FIXME: SDP/infoframe updates aren’t truly atomic, and with the new
+	 * cdclk->tc clock crossing we may transiently send a corrupted packet
+	 * if the update lands mid‑transmission.
+	 */
+	if (!intel_dp_needs_as_sdp(intel_dp, crtc_state))
 		return;
 
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
-- 
2.45.2

[PATCH 10/23] drm/i915/dp: Skip AS SDP for DP branch devices

[Ankit Nautiyal]

Currently, VRR is not implmented for DP branch devices.
So skip sending AS SDP for them.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3d0ea074e610..095bde8e97ef 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3130,6 +3130,12 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	if (!intel_dp->as_sdp_supported)
 		return false;
 
+	/*
+	 * #TODO Implement AS SDP for DP branch device.
+	 */
+	if (drm_dp_is_branch(intel_dp->dpcd))
+		return false;
+
 	return crtc_state->vrr.enable;
 }
 
-- 
2.45.2

[PATCH 11/23] drm/i915/dp: Use revision field of AS SDP data structure

[Ankit Nautiyal]

Use the revision field of struct drm_dp_as_sdp instead of current
hardcoding for the AS SDP revisions.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/display/intel_dp.c      | 7 +++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 10b6c6fcb03f..57870baebfa5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4906,7 +4906,8 @@ static bool
 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
 			const struct drm_dp_as_sdp *b)
 {
-	return a->vtotal == b->vtotal &&
+	return a->revision == b->revision &&
+		a->vtotal == b->vtotal &&
 		a->target_rr == b->target_rr &&
 		a->duration_incr_ms == b->duration_incr_ms &&
 		a->duration_decr_ms == b->duration_decr_ms &&
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 095bde8e97ef..cec0f3d03c2f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3159,6 +3159,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
 	as_sdp->length = 0x9;
 	as_sdp->duration_incr_ms = 0;
+	as_sdp->revision = 0x2;
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
 	if (crtc_state->cmrr.enable) {
@@ -5122,7 +5123,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	/* Prepare AS (Adaptive Sync) SDP Header */
 	sdp->sdp_header.HB0 = 0;
 	sdp->sdp_header.HB1 = as_sdp->sdp_type;
-	sdp->sdp_header.HB2 = 0x02;
+	sdp->sdp_header.HB2 = as_sdp->revision;
 	sdp->sdp_header.HB3 = as_sdp->length;
 
 	/* Fill AS (Adaptive Sync) SDP Payload */
@@ -5309,13 +5310,11 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
 		return -EINVAL;
 
-	if (sdp->sdp_header.HB2 != 0x02)
-		return -EINVAL;
-
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
 	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
+	as_sdp->revision = sdp->sdp_header.HB2;
 	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
-- 
2.45.2

[PATCH 12/23] drm/i915/dp: Include all relevant AS SDP fields in comparison

[Ankit Nautiyal]

Add missing drm_dp_as_sdp header fields to intel_compare_dp_as_sdp()
comparison.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 57870baebfa5..a0e7ef2574b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4906,11 +4906,14 @@ static bool
 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
 			const struct drm_dp_as_sdp *b)
 {
-	return a->revision == b->revision &&
+	return a->sdp_type == b->sdp_type &&
+		a->revision == b->revision &&
+		a->length == b->length &&
 		a->vtotal == b->vtotal &&
 		a->target_rr == b->target_rr &&
 		a->duration_incr_ms == b->duration_incr_ms &&
 		a->duration_decr_ms == b->duration_decr_ms &&
+		a->target_rr_divider == b->target_rr_divider &&
 		a->mode == b->mode;
 }
 
-- 
2.45.2

[PATCH 13/23] drm/i915/psr: Add helper to get Async Video timing support in PR active

[Ankit Nautiyal]

Introduce a helper to check if Panel Replay has Async Video Timing support
during PR Active state.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_psr.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2f1b48cd8efd..782e839b7396 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4623,3 +4623,11 @@ bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state)
 
 	return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr;
 }
+
+bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp)
+{
+	struct intel_connector *connector = intel_dp->attached_connector;
+
+	return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 394b641840b3..29723e63888f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -86,5 +86,6 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *crtc_state);
 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
 bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state);
+bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.45.2

Re: [PATCH 13/23] drm/i915/psr: Add helper to get Async Video timing support in PR active

[Ville Syrjälä]

On Thu, Apr 02, 2026 at 01:34:13PM +0530, Ankit Nautiyal wrote:
> Introduce a helper to check if Panel Replay has Async Video Timing support
> during PR Active state.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
>  drivers/gpu/drm/i915/display/intel_psr.h | 1 +
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2f1b48cd8efd..782e839b7396 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -4623,3 +4623,11 @@ bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state)
>  
>  	return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr;
>  }
> +
> +bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp)
> +{
> +	struct intel_connector *connector = intel_dp->attached_connector;
> +

I think we also need to confirm here that panel replay itself
is supported by the sink. Otherwise this bit will for sure be
zero and then we'll think that we need to transmit AS SDP
even for non-PR sinks.

> +	return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 394b641840b3..29723e63888f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -86,5 +86,6 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>  				   struct intel_crtc_state *crtc_state);
>  int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
>  bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state);
> +bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp);
>  
>  #endif /* __INTEL_PSR_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

[PATCH 14/23] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Ankit Nautiyal]

DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2
(AS SDP v2), which allows the source to set the version in HB2[4:0] and the
payload length in HB3[5:0] of the AS SDP header.

DP v2.1 SCR also introduces ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR in the
Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is set, the sink
does not support asynchronous video timing while in a Panel Replay Active
state and the source is required to keep transmitting Adaptive-Sync
SDPs. The spec mandates that such sinks shall support AS SDP v2.

Infer AS SDP v2 support from these capabilities and store it in
struct intel_dp for use by subsequent feature enablement changes.

v2: Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
    determine AS SDP v2 support. (Ville)
v3: Use helper to determine asynch video timing support.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 33 +++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2496db1642a..efc609eef4f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1870,6 +1870,7 @@ struct intel_dp {
 	/* connector directly attached - won't be use for modeset in mst world */
 	struct intel_connector *attached_connector;
 	bool as_sdp_supported;
+	bool as_sdp_v2_supported;
 
 	struct drm_dp_tunnel *tunnel;
 	bool tunnel_suspended:1;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cec0f3d03c2f..9fd768447f28 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6306,6 +6306,36 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
 					       false);
 }
 
+static bool
+intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
+{
+	u8 rx_features;
+
+	/*
+	 * The DP spec does not explicitly provide the AS SDP v2 capability.
+	 * So based on the DP v2.1 SCR, we infer it from the following bits:
+	 *
+	 * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for
+	 * FAVT, which is explicitly defined to use AS SDP v2.
+	 *
+	 * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR indicates that the sink
+	 * does not support asynchronous video timing while in PR Active,
+	 * requiring the source to keep transmitting Adaptive-Sync SDPs. The
+	 * spec mandates that such sinks shall support AS SDP v2.
+	 */
+	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
+				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
+				  &rx_features) == 1) {
+		if (rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
+			return true;
+	}
+
+	if (!intel_psr_pr_async_video_timing_supported(intel_dp))
+		return true;
+
+	return false;
+}
+
 static void
 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
 {
@@ -6313,6 +6343,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
 
 	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
 		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
+
+	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
+					intel_dp_sink_supports_as_sdp_v2(intel_dp);
 }
 
 static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
-- 
2.45.2

Re: [PATCH 14/23] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Ville Syrjälä]

On Thu, Apr 02, 2026 at 01:34:14PM +0530, Ankit Nautiyal wrote:
> DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
> 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2
> (AS SDP v2), which allows the source to set the version in HB2[4:0] and the
> payload length in HB3[5:0] of the AS SDP header.
> 
> DP v2.1 SCR also introduces ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR in the
> Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is set, the sink
> does not support asynchronous video timing while in a Panel Replay Active
> state and the source is required to keep transmitting Adaptive-Sync
> SDPs. The spec mandates that such sinks shall support AS SDP v2.
> 
> Infer AS SDP v2 support from these capabilities and store it in
> struct intel_dp for use by subsequent feature enablement changes.

Hmm. After some more reading I think we might actually want to consult
the DisplayID for this. The presence of the new adaptive sync block
there might be a good indication for AS SDP v2 support. While the
DisplayID 2.1 spec itself doesn't say that AS SDP v2 must be supported
when the block is present, the DP 2.1 spec does at least say the converse.
Ie. adaptive sync capable DP 2.1 sink must have the DisplayID block. And
DP 2.1 seems to be all about the AS SDP v2 and not AS SDP v1 (that's a DP
2.0 thing really).

I think there was a patch posted very recently on dri-devel, adding the
adaptive sync DisplayID block parsing. Or at least some DisplayID block
related to this.

The intel_psr_pr_async_video_timing_supported() check I think we want
to keep regardless, because you could have a sink with PR but no
adaptive sync. But the FAVT check could perhaps be dropped if we add 
the DisplayID check.

> 
> v2: Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
>     determine AS SDP v2 support. (Ville)
> v3: Use helper to determine asynch video timing support.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 33 +++++++++++++++++++
>  2 files changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e2496db1642a..efc609eef4f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1870,6 +1870,7 @@ struct intel_dp {
>  	/* connector directly attached - won't be use for modeset in mst world */
>  	struct intel_connector *attached_connector;
>  	bool as_sdp_supported;
> +	bool as_sdp_v2_supported;
>  
>  	struct drm_dp_tunnel *tunnel;
>  	bool tunnel_suspended:1;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index cec0f3d03c2f..9fd768447f28 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6306,6 +6306,36 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>  					       false);
>  }
>  
> +static bool
> +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
> +{
> +	u8 rx_features;
> +
> +	/*
> +	 * The DP spec does not explicitly provide the AS SDP v2 capability.
> +	 * So based on the DP v2.1 SCR, we infer it from the following bits:
> +	 *
> +	 * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for
> +	 * FAVT, which is explicitly defined to use AS SDP v2.
> +	 *
> +	 * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR indicates that the sink
> +	 * does not support asynchronous video timing while in PR Active,
> +	 * requiring the source to keep transmitting Adaptive-Sync SDPs. The
> +	 * spec mandates that such sinks shall support AS SDP v2.
> +	 */
> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> +				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
> +				  &rx_features) == 1) {
> +		if (rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
> +			return true;
> +	}
> +
> +	if (!intel_psr_pr_async_video_timing_supported(intel_dp))
> +		return true;
> +
> +	return false;
> +}
> +
>  static void
>  intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>  {
> @@ -6313,6 +6343,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>  
>  	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
>  		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
> +
> +	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
> +					intel_dp_sink_supports_as_sdp_v2(intel_dp);
>  }
>  
>  static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 14/23] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Ville Syrjälä]

On Thu, Apr 02, 2026 at 02:04:28PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 02, 2026 at 01:34:14PM +0530, Ankit Nautiyal wrote:
> > DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
> > 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2
> > (AS SDP v2), which allows the source to set the version in HB2[4:0] and the
> > payload length in HB3[5:0] of the AS SDP header.
> > 
> > DP v2.1 SCR also introduces ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR in the
> > Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is set, the sink
> > does not support asynchronous video timing while in a Panel Replay Active
> > state and the source is required to keep transmitting Adaptive-Sync
> > SDPs. The spec mandates that such sinks shall support AS SDP v2.
> > 
> > Infer AS SDP v2 support from these capabilities and store it in
> > struct intel_dp for use by subsequent feature enablement changes.
> 
> Hmm. After some more reading I think we might actually want to consult
> the DisplayID for this. The presence of the new adaptive sync block
> there might be a good indication for AS SDP v2 support. While the
> DisplayID 2.1 spec itself doesn't say that AS SDP v2 must be supported
> when the block is present, the DP 2.1 spec does at least say the converse.
> Ie. adaptive sync capable DP 2.1 sink must have the DisplayID block. And
> DP 2.1 seems to be all about the AS SDP v2 and not AS SDP v1 (that's a DP
> 2.0 thing really).

Hmm. But the EDID comes from the display, and we could have a PCON
in between that doesn't understand AS SDP v2. Sigh. What a mess.

> 
> I think there was a patch posted very recently on dri-devel, adding the
> adaptive sync DisplayID block parsing. Or at least some DisplayID block
> related to this.
> 
> The intel_psr_pr_async_video_timing_supported() check I think we want
> to keep regardless, because you could have a sink with PR but no
> adaptive sync. But the FAVT check could perhaps be dropped if we add 
> the DisplayID check.
> 
> > 
> > v2: Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
> >     determine AS SDP v2 support. (Ville)
> > v3: Use helper to determine asynch video timing support.
> > 
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  1 +
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 33 +++++++++++++++++++
> >  2 files changed, 34 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index e2496db1642a..efc609eef4f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1870,6 +1870,7 @@ struct intel_dp {
> >  	/* connector directly attached - won't be use for modeset in mst world */
> >  	struct intel_connector *attached_connector;
> >  	bool as_sdp_supported;
> > +	bool as_sdp_v2_supported;
> >  
> >  	struct drm_dp_tunnel *tunnel;
> >  	bool tunnel_suspended:1;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index cec0f3d03c2f..9fd768447f28 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -6306,6 +6306,36 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> >  					       false);
> >  }
> >  
> > +static bool
> > +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
> > +{
> > +	u8 rx_features;
> > +
> > +	/*
> > +	 * The DP spec does not explicitly provide the AS SDP v2 capability.
> > +	 * So based on the DP v2.1 SCR, we infer it from the following bits:
> > +	 *
> > +	 * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for
> > +	 * FAVT, which is explicitly defined to use AS SDP v2.
> > +	 *
> > +	 * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR indicates that the sink
> > +	 * does not support asynchronous video timing while in PR Active,
> > +	 * requiring the source to keep transmitting Adaptive-Sync SDPs. The
> > +	 * spec mandates that such sinks shall support AS SDP v2.
> > +	 */
> > +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> > +				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
> > +				  &rx_features) == 1) {
> > +		if (rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
> > +			return true;
> > +	}
> > +
> > +	if (!intel_psr_pr_async_video_timing_supported(intel_dp))
> > +		return true;
> > +
> > +	return false;
> > +}
> > +
> >  static void
> >  intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
> >  {
> > @@ -6313,6 +6343,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
> >  
> >  	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
> >  		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
> > +
> > +	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
> > +					intel_dp_sink_supports_as_sdp_v2(intel_dp);
> >  }
> >  
> >  static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
> > -- 
> > 2.45.2
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 14/23] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Nautiyal, Ankit K]

On 4/2/2026 6:20 PM, Ville Syrjälä wrote:
> On Thu, Apr 02, 2026 at 02:04:28PM +0300, Ville Syrjälä wrote:
>> On Thu, Apr 02, 2026 at 01:34:14PM +0530, Ankit Nautiyal wrote:
>>> DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
>>> 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2
>>> (AS SDP v2), which allows the source to set the version in HB2[4:0] and the
>>> payload length in HB3[5:0] of the AS SDP header.
>>>
>>> DP v2.1 SCR also introduces ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR in the
>>> Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is set, the sink
>>> does not support asynchronous video timing while in a Panel Replay Active
>>> state and the source is required to keep transmitting Adaptive-Sync
>>> SDPs. The spec mandates that such sinks shall support AS SDP v2.
>>>
>>> Infer AS SDP v2 support from these capabilities and store it in
>>> struct intel_dp for use by subsequent feature enablement changes.
>> Hmm. After some more reading I think we might actually want to consult
>> the DisplayID for this. The presence of the new adaptive sync block
>> there might be a good indication for AS SDP v2 support. While the
>> DisplayID 2.1 spec itself doesn't say that AS SDP v2 must be supported
>> when the block is present, the DP 2.1 spec does at least say the converse.
>> Ie. adaptive sync capable DP 2.1 sink must have the DisplayID block. And
>> DP 2.1 seems to be all about the AS SDP v2 and not AS SDP v1 (that's a DP
>> 2.0 thing really).
> Hmm. But the EDID comes from the display, and we could have a PCON
> in between that doesn't understand AS SDP v2. Sigh. What a mess.


hmm yeah. Is it alright to have a #TODO something like:

/*
* TODO: Check the Adaptive-Sync DisplayID 2.1 block once DisplayID parsing
* is available. This may help detect AS SDP v2 support for native DP 2.1
* sinks that do not expose FAVT or PR-based capability bits.
*
* In the presence of PCONs, check PCON support from DPCD and sink 
support from Display ID.
*/


Regards,

Ankit

>> I think there was a patch posted very recently on dri-devel, adding the
>> adaptive sync DisplayID block parsing. Or at least some DisplayID block
>> related to this.
>>
>> The intel_psr_pr_async_video_timing_supported() check I think we want
>> to keep regardless, because you could have a sink with PR but no
>> adaptive sync. But the FAVT check could perhaps be dropped if we add
>> the DisplayID check.
>>
>>> v2: Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
>>>      determine AS SDP v2 support. (Ville)
>>> v3: Use helper to determine asynch video timing support.
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>>   drivers/gpu/drm/i915/display/intel_dp.c       | 33 +++++++++++++++++++
>>>   2 files changed, 34 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index e2496db1642a..efc609eef4f5 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1870,6 +1870,7 @@ struct intel_dp {
>>>   	/* connector directly attached - won't be use for modeset in mst world */
>>>   	struct intel_connector *attached_connector;
>>>   	bool as_sdp_supported;
>>> +	bool as_sdp_v2_supported;
>>>   
>>>   	struct drm_dp_tunnel *tunnel;
>>>   	bool tunnel_suspended:1;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index cec0f3d03c2f..9fd768447f28 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -6306,6 +6306,36 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>>>   					       false);
>>>   }
>>>   
>>> +static bool
>>> +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
>>> +{
>>> +	u8 rx_features;
>>> +
>>> +	/*
>>> +	 * The DP spec does not explicitly provide the AS SDP v2 capability.
>>> +	 * So based on the DP v2.1 SCR, we infer it from the following bits:
>>> +	 *
>>> +	 * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for
>>> +	 * FAVT, which is explicitly defined to use AS SDP v2.
>>> +	 *
>>> +	 * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR indicates that the sink
>>> +	 * does not support asynchronous video timing while in PR Active,
>>> +	 * requiring the source to keep transmitting Adaptive-Sync SDPs. The
>>> +	 * spec mandates that such sinks shall support AS SDP v2.
>>> +	 */
>>> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
>>> +				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
>>> +				  &rx_features) == 1) {
>>> +		if (rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
>>> +			return true;
>>> +	}
>>> +
>>> +	if (!intel_psr_pr_async_video_timing_supported(intel_dp))
>>> +		return true;
>>> +
>>> +	return false;
>>> +}
>>> +
>>>   static void
>>>   intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>>>   {
>>> @@ -6313,6 +6343,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>>>   
>>>   	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
>>>   		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
>>> +
>>> +	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
>>> +					intel_dp_sink_supports_as_sdp_v2(intel_dp);
>>>   }
>>>   
>>>   static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
>>> -- 
>>> 2.45.2
>> -- 
>> Ville Syrjälä
>> Intel

Re: [PATCH 14/23] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Nautiyal, Ankit K]

On 4/7/2026 1:50 PM, Nautiyal, Ankit K wrote:
>
> On 4/2/2026 6:20 PM, Ville Syrjälä wrote:
>> On Thu, Apr 02, 2026 at 02:04:28PM +0300, Ville Syrjälä wrote:
>>> On Thu, Apr 02, 2026 at 01:34:14PM +0530, Ankit Nautiyal wrote:
>>>> DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
>>>> 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP 
>>>> version 2
>>>> (AS SDP v2), which allows the source to set the version in HB2[4:0] 
>>>> and the
>>>> payload length in HB3[5:0] of the AS SDP header.
>>>>
>>>> DP v2.1 SCR also introduces ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR 
>>>> in the
>>>> Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is set, 
>>>> the sink
>>>> does not support asynchronous video timing while in a Panel Replay 
>>>> Active
>>>> state and the source is required to keep transmitting Adaptive-Sync
>>>> SDPs. The spec mandates that such sinks shall support AS SDP v2.
>>>>
>>>> Infer AS SDP v2 support from these capabilities and store it in
>>>> struct intel_dp for use by subsequent feature enablement changes.
>>> Hmm. After some more reading I think we might actually want to consult
>>> the DisplayID for this. The presence of the new adaptive sync block
>>> there might be a good indication for AS SDP v2 support. While the
>>> DisplayID 2.1 spec itself doesn't say that AS SDP v2 must be supported
>>> when the block is present, the DP 2.1 spec does at least say the 
>>> converse.
>>> Ie. adaptive sync capable DP 2.1 sink must have the DisplayID block. 
>>> And
>>> DP 2.1 seems to be all about the AS SDP v2 and not AS SDP v1 (that's 
>>> a DP
>>> 2.0 thing really).
>> Hmm. But the EDID comes from the display, and we could have a PCON
>> in between that doesn't understand AS SDP v2. Sigh. What a mess.
>
>
> hmm yeah. Is it alright to have a #TODO something like:
>
> /*
> * TODO: Check the Adaptive-Sync DisplayID 2.1 block once DisplayID 
> parsing
> * is available. This may help detect AS SDP v2 support for native DP 2.1
> * sinks that do not expose FAVT or PR-based capability bits.
> *
> * In the presence of PCONs, check PCON support from DPCD and sink 
> support from Display ID.
> */
>

Going throught the eDP spec, it seems for eDP,  if AS SDP is supported 
it implicitly means AS SDP v2.

 From eDP spec 2.0

Section 2.8 Adaptive-Sync

"eDP may optionally support the Adaptive-Sync operation to maintain 
video timing
synchronization between Source and Sink devices (see DP Standard, 
“Adaptive-Sync Operation
for VESA AdaptiveSync”). If supported, the Adaptive-Sync SDP version 
shall be v2 or higher
(HB2[4:0] = 02h or higher, and HB3[5:0] = 09h or higher)."

Also, the FAVT Payload fields parsing support is not used for eDP and 
will always read 0.

This however doesn't mean that FAVT is not supported, the support is 
implicit.

Section 8.7.1 Video Timing Synchronization while in a PR Active State
with ALPM Enabled

...Source-to-Sink device timing synchronization during a PR Active state 
that uses the Adaptive-Sync SDP may be enabled in
Adaptive-Sync (FAVT or AVT mode) operation (DPCD 00107h[7] = 1) –or– when
DPCD 00107h[7] = 0..


So, I will update the logic for eDP here.

Regards,

Ankit



>
> Regards,
>
> Ankit
>
>>> I think there was a patch posted very recently on dri-devel, adding the
>>> adaptive sync DisplayID block parsing. Or at least some DisplayID block
>>> related to this.
>>>
>>> The intel_psr_pr_async_video_timing_supported() check I think we want
>>> to keep regardless, because you could have a sink with PR but no
>>> adaptive sync. But the FAVT check could perhaps be dropped if we add
>>> the DisplayID check.
>>>
>>>> v2: Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
>>>>      determine AS SDP v2 support. (Ville)
>>>> v3: Use helper to determine asynch video timing support.
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>>>   drivers/gpu/drm/i915/display/intel_dp.c       | 33 
>>>> +++++++++++++++++++
>>>>   2 files changed, 34 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
>>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> index e2496db1642a..efc609eef4f5 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> @@ -1870,6 +1870,7 @@ struct intel_dp {
>>>>       /* connector directly attached - won't be use for modeset in 
>>>> mst world */
>>>>       struct intel_connector *attached_connector;
>>>>       bool as_sdp_supported;
>>>> +    bool as_sdp_v2_supported;
>>>>         struct drm_dp_tunnel *tunnel;
>>>>       bool tunnel_suspended:1;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
>>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index cec0f3d03c2f..9fd768447f28 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -6306,6 +6306,36 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>>>>                              false);
>>>>   }
>>>>   +static bool
>>>> +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
>>>> +{
>>>> +    u8 rx_features;
>>>> +
>>>> +    /*
>>>> +     * The DP spec does not explicitly provide the AS SDP v2 
>>>> capability.
>>>> +     * So based on the DP v2.1 SCR, we infer it from the following 
>>>> bits:
>>>> +     *
>>>> +     * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates 
>>>> support for
>>>> +     * FAVT, which is explicitly defined to use AS SDP v2.
>>>> +     *
>>>> +     * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR indicates that 
>>>> the sink
>>>> +     * does not support asynchronous video timing while in PR Active,
>>>> +     * requiring the source to keep transmitting Adaptive-Sync 
>>>> SDPs. The
>>>> +     * spec mandates that such sinks shall support AS SDP v2.
>>>> +     */
>>>> +    if (drm_dp_dpcd_read_byte(&intel_dp->aux,
>>>> +                  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
>>>> +                  &rx_features) == 1) {
>>>> +        if (rx_features & 
>>>> DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
>>>> +            return true;
>>>> +    }
>>>> +
>>>> +    if (!intel_psr_pr_async_video_timing_supported(intel_dp))
>>>> +        return true;
>>>> +
>>>> +    return false;
>>>> +}
>>>> +
>>>>   static void
>>>>   intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>>>>   {
>>>> @@ -6313,6 +6343,9 @@ intel_dp_detect_sdp_caps(struct intel_dp 
>>>> *intel_dp)
>>>>         intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
>>>>           drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
>>>> +
>>>> +    intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
>>>> + intel_dp_sink_supports_as_sdp_v2(intel_dp);
>>>>   }
>>>>     static bool intel_dp_needs_dpcd_probe(struct intel_dp 
>>>> *intel_dp, bool force_on_external)
>>>> -- 
>>>> 2.45.2
>>> -- 
>>> Ville Syrjälä
>>> Intel

Re: [PATCH 14/23] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Ville Syrjälä]

On Tue, Apr 07, 2026 at 07:05:51PM +0530, Nautiyal, Ankit K wrote:
> 
> On 4/7/2026 1:50 PM, Nautiyal, Ankit K wrote:
> >
> > On 4/2/2026 6:20 PM, Ville Syrjälä wrote:
> >> On Thu, Apr 02, 2026 at 02:04:28PM +0300, Ville Syrjälä wrote:
> >>> On Thu, Apr 02, 2026 at 01:34:14PM +0530, Ankit Nautiyal wrote:
> >>>> DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
> >>>> 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP 
> >>>> version 2
> >>>> (AS SDP v2), which allows the source to set the version in HB2[4:0] 
> >>>> and the
> >>>> payload length in HB3[5:0] of the AS SDP header.
> >>>>
> >>>> DP v2.1 SCR also introduces ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR 
> >>>> in the
> >>>> Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is set, 
> >>>> the sink
> >>>> does not support asynchronous video timing while in a Panel Replay 
> >>>> Active
> >>>> state and the source is required to keep transmitting Adaptive-Sync
> >>>> SDPs. The spec mandates that such sinks shall support AS SDP v2.
> >>>>
> >>>> Infer AS SDP v2 support from these capabilities and store it in
> >>>> struct intel_dp for use by subsequent feature enablement changes.
> >>> Hmm. After some more reading I think we might actually want to consult
> >>> the DisplayID for this. The presence of the new adaptive sync block
> >>> there might be a good indication for AS SDP v2 support. While the
> >>> DisplayID 2.1 spec itself doesn't say that AS SDP v2 must be supported
> >>> when the block is present, the DP 2.1 spec does at least say the 
> >>> converse.
> >>> Ie. adaptive sync capable DP 2.1 sink must have the DisplayID block. 
> >>> And
> >>> DP 2.1 seems to be all about the AS SDP v2 and not AS SDP v1 (that's 
> >>> a DP
> >>> 2.0 thing really).
> >> Hmm. But the EDID comes from the display, and we could have a PCON
> >> in between that doesn't understand AS SDP v2. Sigh. What a mess.
> >
> >
> > hmm yeah. Is it alright to have a #TODO something like:
> >
> > /*
> > * TODO: Check the Adaptive-Sync DisplayID 2.1 block once DisplayID 
> > parsing
> > * is available. This may help detect AS SDP v2 support for native DP 2.1
> > * sinks that do not expose FAVT or PR-based capability bits.
> > *
> > * In the presence of PCONs, check PCON support from DPCD and sink 
> > support from Display ID.
> > */
> >
> 
> Going throught the eDP spec, it seems for eDP,  if AS SDP is supported 
> it implicitly means AS SDP v2.
> 
>  From eDP spec 2.0

eDP 2.0 does not seem relevant for us. But IIRC eDP v1.5 also implies
AS SDP v2 support. And that we can actually check if necessary.

Though I suppose the only real concern is branch devices. Maybe we
should use the FAVT check only for those. For everything else it
should be sufficient to have either the DisplayID adaptive sync 
block or PR ALPM support.

> 
> Section 2.8 Adaptive-Sync
> 
> "eDP may optionally support the Adaptive-Sync operation to maintain 
> video timing
> synchronization between Source and Sink devices (see DP Standard, 
> “Adaptive-Sync Operation
> for VESA AdaptiveSync”). If supported, the Adaptive-Sync SDP version 
> shall be v2 or higher
> (HB2[4:0] = 02h or higher, and HB3[5:0] = 09h or higher)."
> 
> Also, the FAVT Payload fields parsing support is not used for eDP and 
> will always read 0.
> 
> This however doesn't mean that FAVT is not supported, the support is 
> implicit.
> 
> Section 8.7.1 Video Timing Synchronization while in a PR Active State
> with ALPM Enabled
> 
> ...Source-to-Sink device timing synchronization during a PR Active state 
> that uses the Adaptive-Sync SDP may be enabled in
> Adaptive-Sync (FAVT or AVT mode) operation (DPCD 00107h[7] = 1) –or– when
> DPCD 00107h[7] = 0..
> 
> 
> So, I will update the logic for eDP here.
> 
> Regards,
> 
> Ankit
> 
> 
> 
> >
> > Regards,
> >
> > Ankit
> >
> >>> I think there was a patch posted very recently on dri-devel, adding the
> >>> adaptive sync DisplayID block parsing. Or at least some DisplayID block
> >>> related to this.
> >>>
> >>> The intel_psr_pr_async_video_timing_supported() check I think we want
> >>> to keep regardless, because you could have a sink with PR but no
> >>> adaptive sync. But the FAVT check could perhaps be dropped if we add
> >>> the DisplayID check.
> >>>
> >>>> v2: Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
> >>>>      determine AS SDP v2 support. (Ville)
> >>>> v3: Use helper to determine asynch video timing support.
> >>>>
> >>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >>>> ---
> >>>>   .../drm/i915/display/intel_display_types.h    |  1 +
> >>>>   drivers/gpu/drm/i915/display/intel_dp.c       | 33 
> >>>> +++++++++++++++++++
> >>>>   2 files changed, 34 insertions(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> >>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>> index e2496db1642a..efc609eef4f5 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>> @@ -1870,6 +1870,7 @@ struct intel_dp {
> >>>>       /* connector directly attached - won't be use for modeset in 
> >>>> mst world */
> >>>>       struct intel_connector *attached_connector;
> >>>>       bool as_sdp_supported;
> >>>> +    bool as_sdp_v2_supported;
> >>>>         struct drm_dp_tunnel *tunnel;
> >>>>       bool tunnel_suspended:1;
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> >>>> b/drivers/gpu/drm/i915/display/intel_dp.c
> >>>> index cec0f3d03c2f..9fd768447f28 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >>>> @@ -6306,6 +6306,36 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> >>>>                              false);
> >>>>   }
> >>>>   +static bool
> >>>> +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
> >>>> +{
> >>>> +    u8 rx_features;
> >>>> +
> >>>> +    /*
> >>>> +     * The DP spec does not explicitly provide the AS SDP v2 
> >>>> capability.
> >>>> +     * So based on the DP v2.1 SCR, we infer it from the following 
> >>>> bits:
> >>>> +     *
> >>>> +     * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates 
> >>>> support for
> >>>> +     * FAVT, which is explicitly defined to use AS SDP v2.
> >>>> +     *
> >>>> +     * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR indicates that 
> >>>> the sink
> >>>> +     * does not support asynchronous video timing while in PR Active,
> >>>> +     * requiring the source to keep transmitting Adaptive-Sync 
> >>>> SDPs. The
> >>>> +     * spec mandates that such sinks shall support AS SDP v2.
> >>>> +     */
> >>>> +    if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> >>>> +                  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
> >>>> +                  &rx_features) == 1) {
> >>>> +        if (rx_features & 
> >>>> DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
> >>>> +            return true;
> >>>> +    }
> >>>> +
> >>>> +    if (!intel_psr_pr_async_video_timing_supported(intel_dp))
> >>>> +        return true;
> >>>> +
> >>>> +    return false;
> >>>> +}
> >>>> +
> >>>>   static void
> >>>>   intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
> >>>>   {
> >>>> @@ -6313,6 +6343,9 @@ intel_dp_detect_sdp_caps(struct intel_dp 
> >>>> *intel_dp)
> >>>>         intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
> >>>>           drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
> >>>> +
> >>>> +    intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
> >>>> + intel_dp_sink_supports_as_sdp_v2(intel_dp);
> >>>>   }
> >>>>     static bool intel_dp_needs_dpcd_probe(struct intel_dp 
> >>>> *intel_dp, bool force_on_external)
> >>>> -- 
> >>>> 2.45.2
> >>> -- 
> >>> Ville Syrjälä
> >>> Intel

-- 
Ville Syrjälä
Intel

[PATCH 15/23] drm/i915/dp: Allow AS SDP only if v2 is supported

[Ankit Nautiyal]

We do not support AS SDP version 1, so allow AS SDP only if AS SDP v2 is
supported.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9fd768447f28..e97233805348 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3127,7 +3127,7 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 				  struct intel_crtc_state *crtc_state)
 {
-	if (!intel_dp->as_sdp_supported)
+	if (!intel_dp->as_sdp_v2_supported)
 		return false;
 
 	/*
-- 
2.45.2

[PATCH 16/23] drm/i915/psr: Write the PR config DPCDs in burst mode

[Ankit Nautiyal]

Replace the consecutive single-byte writes to PANEL_REPLAY_CONFIG and
CONFIG2 with one drm_dp_dpcd_write() burst starting at PANEL_REPLAY_CONFIG,
reducing AUX transactions.

v2: Drop extra conditions, and optimize variables. (Ville)
v3: Drop the error check after write. (Ville)

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 26 ++++++++++++------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 782e839b7396..3fe7691c8b77 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -782,27 +782,27 @@ static bool psr2_su_region_et_valid(struct intel_connector *connector, bool pane
 static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 				      const struct intel_crtc_state *crtc_state)
 {
-	u8 val = DP_PANEL_REPLAY_ENABLE |
-		DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
-		DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
-		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
-		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
-	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
+	u8 panel_replay_config[2];
+
+	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
+				 DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
+				 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
+				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
+				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
+	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
 
 	if (crtc_state->has_sel_update)
-		val |= DP_PANEL_REPLAY_SU_ENABLE;
+		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
 
 	if (crtc_state->enable_psr2_su_region_et)
-		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
+		panel_replay_config[0] |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
 
 	if (crtc_state->req_psr2_sdp_prior_scanline)
-		panel_replay_config2 |=
+		panel_replay_config[1] |=
 			DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
 
-	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
-
-	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
-			   panel_replay_config2);
+	drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+			  panel_replay_config, sizeof(panel_replay_config));
 }
 
 static void _psr_enable_sink(struct intel_dp *intel_dp,
-- 
2.45.2

[PATCH 17/23] drm/i915/display: Add helper for AS SDP transmission time selection

[Ankit Nautiyal]

AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
Adaptive Sync SDP configuration as per DP 2.1. Current we are using
T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
selection.

Introduce a helper to return the appropriate AS SDP transmission time so
that a single value is consistently used for programming PR_ALPM.
For now this returns T1.

v2: Avoid adding new member to crtc_state; use a helper. (Ville)
v3: Clarify why AS SDP transmission time is fixed to T1. (Ville)
v4: Return u8 from intel_dp_as_sdp_transmission_time(). (Ville)

Bspec: 68920
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.c   | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h   |  2 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index a7350ce8e716..c6963ea420cc 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -11,6 +11,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_display_utils.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
 #include "intel_psr.h"
@@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	crtc_state->has_lobf = true;
 }
 
+static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
+{
+	u8 as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
+
+	switch (as_sdp_setup_time) {
+	case DP_PR_AS_SDP_SETUP_TIME_T1:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+	case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
+	case DP_PR_AS_SDP_SETUP_TIME_T2:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
+	default:
+		MISSING_CASE(as_sdp_setup_time);
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+	}
+}
+
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
 {
@@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
 
 		if (intel_dp->as_sdp_supported) {
-			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
 
 			if (crtc_state->link_off_after_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e97233805348..87388694ce17 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7466,3 +7466,14 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 	return true;
 }
+
+u8 intel_dp_as_sdp_transmission_time(void)
+{
+	/*
+	 * DP allows AS SDP position to move during PR active in some cases, but
+	 * software-controlled refresh rate changes with DC6v / ALPM require the
+	 * AS SDP to remain at T1. Use T1 unconditionally for now.
+	 */
+
+	return DP_PR_AS_SDP_SETUP_TIME_T1;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 2849b9ecdc71..66e7a89bcb64 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
 		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
+u8 intel_dp_as_sdp_transmission_time(void);
+
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2

[PATCH 18/23] drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time

[Ankit Nautiyal]

Panel Replay requires the AS SDP transmission time to be written into
PANEL_REPLAY_CONFIG3. This field was previously not programmed.

Use the AS SDP transmission-time helper to populate CONFIG3.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3fe7691c8b77..a9032b7ff814 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -783,6 +783,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 				      const struct intel_crtc_state *crtc_state)
 {
 	u8 panel_replay_config[2];
+	u8 panel_replay_config_3;
 
 	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
 				 DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
@@ -790,7 +791,6 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
 				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
 	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
-
 	if (crtc_state->has_sel_update)
 		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
 
@@ -803,6 +803,9 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 
 	drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG,
 			  panel_replay_config, sizeof(panel_replay_config));
+
+	panel_replay_config_3 = intel_dp_as_sdp_transmission_time();
+	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3, panel_replay_config_3);
 }
 
 static void _psr_enable_sink(struct intel_dp *intel_dp,
-- 
2.45.2

Re: [PATCH 18/23] drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time

[Ville Syrjälä]

On Thu, Apr 02, 2026 at 01:34:18PM +0530, Ankit Nautiyal wrote:
> Panel Replay requires the AS SDP transmission time to be written into
> PANEL_REPLAY_CONFIG3. This field was previously not programmed.
> 
> Use the AS SDP transmission-time helper to populate CONFIG3.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 3fe7691c8b77..a9032b7ff814 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -783,6 +783,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>  				      const struct intel_crtc_state *crtc_state)
>  {
>  	u8 panel_replay_config[2];
> +	u8 panel_replay_config_3;
>  
>  	panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
>  				 DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
> @@ -790,7 +791,6 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>  				 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
>  				 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
>  	panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
> -
>  	if (crtc_state->has_sel_update)
>  		panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
>  
> @@ -803,6 +803,9 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>  
>  	drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG,
>  			  panel_replay_config, sizeof(panel_replay_config));
> +
> +	panel_replay_config_3 = intel_dp_as_sdp_transmission_time();
> +	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3, panel_replay_config_3);
>  }
>  
>  static void _psr_enable_sink(struct intel_dp *intel_dp,
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

[PATCH 19/23] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Ankit Nautiyal]

If a Panel Replay capable sink, supports Async Video timing in
PR active state, then source does not necessarily need to send AS SDPs
during PR active.

However, if asynchronous video timing is not supported, then for PR with
Aux-less ALPM, the source must transmit Adaptive-Sync SDPs for video
timing synchronization while PR is active.

If the source needs to send AS SDP during PR active, this requires setting
DPCD 0x0107[6] (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether
VRR is enabled (AVT/FAVT) or fixed-timing mode is used.

This bit defines AS SDP timing behavior during PR Active, even if AS SDPs
are briefly suspended.

Program the relevant Downspread Ctrl DPCD bits accordingly.

v2: Instead of Panel Replay check simply use AS SDP enable check. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++++++--
 .../gpu/drm/i915/display/intel_dp_link_training.h    |  3 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c          |  2 +-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a26094223f78..8b21c479ebfc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -27,6 +27,7 @@
 #include <drm/display/drm_dp_helper.h>
 #include <drm/drm_print.h>
 
+#include "intel_alpm.h"
 #include "intel_display_core.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_types.h"
@@ -34,6 +35,7 @@
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
 #include "intel_encoder.h"
+#include "intel_hdmi.h"
 #include "intel_hotplug.h"
 #include "intel_panel.h"
 
@@ -710,11 +712,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
 	return true;
 }
 
-void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
+void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
+				     bool is_vrr,
+				     bool as_sdp_enable)
 {
 	u8 link_config[2];
 
 	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+	link_config[0] |= as_sdp_enable ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
 	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
 			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
@@ -737,7 +742,10 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 	  * especially on the first real commit when clearing the inherited flag.
 	  */
 	intel_dp_link_training_set_mode(intel_dp,
-					crtc_state->port_clock, crtc_state->vrr.in_range);
+					crtc_state->port_clock,
+					crtc_state->vrr.in_range,
+					crtc_state->infoframes.enable &
+					intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC));
 }
 
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 33dcbde6a408..d3ae8ee38a75 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
 bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
 
 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
-				     int link_rate, bool is_vrr);
+				     int link_rate, bool is_vrr,
+				     bool as_sdp_enable);
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 				   int link_bw, int rate_select, int lane_count,
 				   bool enhanced_framing, bool post_lt_adj_req);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e8de17834dcd..ffd1cf0aad9a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
 
 	intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
 
-	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
+	intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
 	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
 				      drm_dp_enhanced_frame_cap(intel_dp->dpcd), false);
 
-- 
2.45.2

Re: [PATCH 19/23] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Ville Syrjälä]

On Thu, Apr 02, 2026 at 01:34:19PM +0530, Ankit Nautiyal wrote:
> If a Panel Replay capable sink, supports Async Video timing in
> PR active state, then source does not necessarily need to send AS SDPs
> during PR active.
> 
> However, if asynchronous video timing is not supported, then for PR with
> Aux-less ALPM, the source must transmit Adaptive-Sync SDPs for video
> timing synchronization while PR is active.
> 
> If the source needs to send AS SDP during PR active, this requires setting
> DPCD 0x0107[6] (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether
> VRR is enabled (AVT/FAVT) or fixed-timing mode is used.
> 
> This bit defines AS SDP timing behavior during PR Active, even if AS SDPs
> are briefly suspended.
> 
> Program the relevant Downspread Ctrl DPCD bits accordingly.
> 
> v2: Instead of Panel Replay check simply use AS SDP enable check. (Ville)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++++++--
>  .../gpu/drm/i915/display/intel_dp_link_training.h    |  3 ++-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c          |  2 +-
>  3 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index a26094223f78..8b21c479ebfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -27,6 +27,7 @@
>  #include <drm/display/drm_dp_helper.h>
>  #include <drm/drm_print.h>
>  
> +#include "intel_alpm.h"
>  #include "intel_display_core.h"
>  #include "intel_display_jiffies.h"
>  #include "intel_display_types.h"
> @@ -34,6 +35,7 @@
>  #include "intel_dp.h"
>  #include "intel_dp_link_training.h"
>  #include "intel_encoder.h"
> +#include "intel_hdmi.h"
>  #include "intel_hotplug.h"
>  #include "intel_panel.h"
>  
> @@ -710,11 +712,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> -void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
> +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
> +				     bool is_vrr,
> +				     bool as_sdp_enable)
>  {
>  	u8 link_config[2];
>  
>  	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> +	link_config[0] |= as_sdp_enable ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
>  	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
>  			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>  	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> @@ -737,7 +742,10 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>  	  * especially on the first real commit when clearing the inherited flag.
>  	  */
>  	intel_dp_link_training_set_mode(intel_dp,
> -					crtc_state->port_clock, crtc_state->vrr.in_range);
> +					crtc_state->port_clock,
> +					crtc_state->vrr.in_range,
> +					crtc_state->infoframes.enable &
> +					intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC));

The bit is only documented to be valid for panel replay capable
sinks. So we should probably not set it otherwise.

But the weird thing is that the AS SDP DB0[1:0] description does not
provide for a set of valid values for that case (DPCD 107h[7:6]=10b).
Either they assumed that AS SDP v1 is used in that case (in which case
the we'd not be able to support FAVT and maybe some other stuff without
PR), or it's just an oversight and the same values apply as for
107h[7:6]=10b as they do for 107h[7:6]=11b.

>  }
>  
>  void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 33dcbde6a408..d3ae8ee38a75 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
>  bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
>  
>  void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
> -				     int link_rate, bool is_vrr);
> +				     int link_rate, bool is_vrr,
> +				     bool as_sdp_enable);
>  void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>  				   int link_bw, int rate_select, int lane_count,
>  				   bool enhanced_framing, bool post_lt_adj_req);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index e8de17834dcd..ffd1cf0aad9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
>  
>  	intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
>  
> -	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
> +	intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
>  	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
>  				      drm_dp_enhanced_frame_cap(intel_dp->dpcd), false);
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 19/23] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Nautiyal, Ankit K]

On 4/2/2026 4:18 PM, Ville Syrjälä wrote:
> On Thu, Apr 02, 2026 at 01:34:19PM +0530, Ankit Nautiyal wrote:
>> If a Panel Replay capable sink, supports Async Video timing in
>> PR active state, then source does not necessarily need to send AS SDPs
>> during PR active.
>>
>> However, if asynchronous video timing is not supported, then for PR with
>> Aux-less ALPM, the source must transmit Adaptive-Sync SDPs for video
>> timing synchronization while PR is active.
>>
>> If the source needs to send AS SDP during PR active, this requires setting
>> DPCD 0x0107[6] (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether
>> VRR is enabled (AVT/FAVT) or fixed-timing mode is used.
>>
>> This bit defines AS SDP timing behavior during PR Active, even if AS SDPs
>> are briefly suspended.
>>
>> Program the relevant Downspread Ctrl DPCD bits accordingly.
>>
>> v2: Instead of Panel Replay check simply use AS SDP enable check. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++++++--
>>   .../gpu/drm/i915/display/intel_dp_link_training.h    |  3 ++-
>>   drivers/gpu/drm/i915/display/intel_dp_mst.c          |  2 +-
>>   3 files changed, 13 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index a26094223f78..8b21c479ebfc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -27,6 +27,7 @@
>>   #include <drm/display/drm_dp_helper.h>
>>   #include <drm/drm_print.h>
>>   
>> +#include "intel_alpm.h"
>>   #include "intel_display_core.h"
>>   #include "intel_display_jiffies.h"
>>   #include "intel_display_types.h"
>> @@ -34,6 +35,7 @@
>>   #include "intel_dp.h"
>>   #include "intel_dp_link_training.h"
>>   #include "intel_encoder.h"
>> +#include "intel_hdmi.h"
>>   #include "intel_hotplug.h"
>>   #include "intel_panel.h"
>>   
>> @@ -710,11 +712,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
>>   	return true;
>>   }
>>   
>> -void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
>> +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
>> +				     bool is_vrr,
>> +				     bool as_sdp_enable)
>>   {
>>   	u8 link_config[2];
>>   
>>   	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> +	link_config[0] |= as_sdp_enable ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
>>   	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
>>   			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>>   	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>> @@ -737,7 +742,10 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>>   	  * especially on the first real commit when clearing the inherited flag.
>>   	  */
>>   	intel_dp_link_training_set_mode(intel_dp,
>> -					crtc_state->port_clock, crtc_state->vrr.in_range);
>> +					crtc_state->port_clock,
>> +					crtc_state->vrr.in_range,
>> +					crtc_state->infoframes.enable &
>> +					intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC));
> The bit is only documented to be valid for panel replay capable
> sinks. So we should probably not set it otherwise.
>
> But the weird thing is that the AS SDP DB0[1:0] description does not
> provide for a set of valid values for that case (DPCD 107h[7:6]=10b).
> Either they assumed that AS SDP v1 is used in that case (in which case
> the we'd not be able to support FAVT and maybe some other stuff without
> PR), or it's just an oversight and the same values apply as for
> 107h[7:6]=10b as they do for 107h[7:6]=11b.


Yeah you are right, the spec doesnt say any specific thing for AS SDP 
DB0[1:0] when DPCD 107h[7:6]=10b.

It says for values 11b and 01b. As you said, I agree we should have a 
Panel Replay check also.

I'll just use:

intel_alpm_is_alpm_aux_less() &&
crtc_state->infoframes.enable & 
intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))


Regards,

Ankit

>
>>   }
>>   
>>   void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> index 33dcbde6a408..d3ae8ee38a75 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> @@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
>>   bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
>>   
>>   void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
>> -				     int link_rate, bool is_vrr);
>> +				     int link_rate, bool is_vrr,
>> +				     bool as_sdp_enable);
>>   void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>>   				   int link_bw, int rate_select, int lane_count,
>>   				   bool enhanced_framing, bool post_lt_adj_req);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index e8de17834dcd..ffd1cf0aad9a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
>>   
>>   	intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
>>   
>> -	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
>> +	intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
>>   	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
>>   				      drm_dp_enhanced_frame_cap(intel_dp->dpcd), false);
>>   
>> -- 
>> 2.45.2

Re: [PATCH 19/23] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Nautiyal, Ankit K]

On 4/7/2026 2:21 PM, Nautiyal, Ankit K wrote:
>
> On 4/2/2026 4:18 PM, Ville Syrjälä wrote:
>> On Thu, Apr 02, 2026 at 01:34:19PM +0530, Ankit Nautiyal wrote:
>>> If a Panel Replay capable sink, supports Async Video timing in
>>> PR active state, then source does not necessarily need to send AS SDPs
>>> during PR active.
>>>
>>> However, if asynchronous video timing is not supported, then for PR 
>>> with
>>> Aux-less ALPM, the source must transmit Adaptive-Sync SDPs for video
>>> timing synchronization while PR is active.
>>>
>>> If the source needs to send AS SDP during PR active, this requires 
>>> setting
>>> DPCD 0x0107[6] (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies 
>>> whether
>>> VRR is enabled (AVT/FAVT) or fixed-timing mode is used.
>>>
>>> This bit defines AS SDP timing behavior during PR Active, even if AS 
>>> SDPs
>>> are briefly suspended.
>>>
>>> Program the relevant Downspread Ctrl DPCD bits accordingly.
>>>
>>> v2: Instead of Panel Replay check simply use AS SDP enable check. 
>>> (Ville)
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 
>>> ++++++++++--
>>>   .../gpu/drm/i915/display/intel_dp_link_training.h    |  3 ++-
>>>   drivers/gpu/drm/i915/display/intel_dp_mst.c          |  2 +-
>>>   3 files changed, 13 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c 
>>> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> index a26094223f78..8b21c479ebfc 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> @@ -27,6 +27,7 @@
>>>   #include <drm/display/drm_dp_helper.h>
>>>   #include <drm/drm_print.h>
>>>   +#include "intel_alpm.h"
>>>   #include "intel_display_core.h"
>>>   #include "intel_display_jiffies.h"
>>>   #include "intel_display_types.h"
>>> @@ -34,6 +35,7 @@
>>>   #include "intel_dp.h"
>>>   #include "intel_dp_link_training.h"
>>>   #include "intel_encoder.h"
>>> +#include "intel_hdmi.h"
>>>   #include "intel_hotplug.h"
>>>   #include "intel_panel.h"
>>>   @@ -710,11 +712,14 @@ static bool 
>>> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
>>>       return true;
>>>   }
>>>   -void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, 
>>> int link_rate, bool is_vrr)
>>> +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int 
>>> link_rate,
>>> +                     bool is_vrr,
>>> +                     bool as_sdp_enable)
>>>   {
>>>       u8 link_config[2];
>>>         link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>>> +    link_config[0] |= as_sdp_enable ? 
>>> DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
>>>       link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
>>>                DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>>>       drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 
>>> link_config, 2);
>>> @@ -737,7 +742,10 @@ static void 
>>> intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>>>         * especially on the first real commit when clearing the 
>>> inherited flag.
>>>         */
>>>       intel_dp_link_training_set_mode(intel_dp,
>>> -                    crtc_state->port_clock, crtc_state->vrr.in_range);
>>> +                    crtc_state->port_clock,
>>> +                    crtc_state->vrr.in_range,
>>> +                    crtc_state->infoframes.enable &
>>> + intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC));
>> The bit is only documented to be valid for panel replay capable
>> sinks. So we should probably not set it otherwise.
>>
>> But the weird thing is that the AS SDP DB0[1:0] description does not
>> provide for a set of valid values for that case (DPCD 107h[7:6]=10b).
>> Either they assumed that AS SDP v1 is used in that case (in which case
>> the we'd not be able to support FAVT and maybe some other stuff without
>> PR), or it's just an oversight and the same values apply as for
>> 107h[7:6]=10b as they do for 107h[7:6]=11b.
>
>
> Yeah you are right, the spec doesnt say any specific thing for AS SDP 
> DB0[1:0] when DPCD 107h[7:6]=10b.
>
> It says for values 11b and 01b. As you said, I agree we should have a 
> Panel Replay check also.
>
> I'll just use:
>
> intel_alpm_is_alpm_aux_less() &&


I think I need to use intel_psr_needs_alpm_aux_less()  instead.



> crtc_state->infoframes.enable & 
> intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
>
>
> Regards,
>
> Ankit
>
>>
>>>   }
>>>     void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h 
>>> b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>>> index 33dcbde6a408..d3ae8ee38a75 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>>> @@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct 
>>> intel_dp *intel_dp);
>>>   bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp 
>>> *intel_dp);
>>>     void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
>>> -                     int link_rate, bool is_vrr);
>>> +                     int link_rate, bool is_vrr,
>>> +                     bool as_sdp_enable);
>>>   void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>>>                      int link_bw, int rate_select, int lane_count,
>>>                      bool enhanced_framing, bool post_lt_adj_req);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
>>> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>>> index e8de17834dcd..ffd1cf0aad9a 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>>> @@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct 
>>> intel_dp *intel_dp)
>>>         intel_dp_compute_rate(intel_dp, link_rate, &link_bw, 
>>> &rate_select);
>>>   -    intel_dp_link_training_set_mode(intel_dp, link_rate, false);
>>> +    intel_dp_link_training_set_mode(intel_dp, link_rate, false, 
>>> false);
>>>       intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, 
>>> lane_count,
>>> drm_dp_enhanced_frame_cap(intel_dp->dpcd), false);
>>>   --
>>> 2.45.2

[PATCH 20/23] drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off

[Ankit Nautiyal]

For Panel Replay with AUX-less ALPM (link-off PR), the source must send
Adaptive-Sync SDP v2. Program DB[1:0] per DP spec v2.1:
- VRR AVT: 00b (variable VTotal)
- VRR FAVT: 10b/11b (TRR not reached/reached)
- Fixed timing with PR link-off (VRR off): 01b (AS disabled; VTotal fixed)

Also, drop the redundant target_rr assignment.

v2: Fix the else case. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 87388694ce17..ddaa187371b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3166,9 +3166,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 		as_sdp->target_rr_divider = true;
-	} else {
+	} else if (crtc_state->vrr.enable) {
 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-		as_sdp->target_rr = 0;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
 	}
 }
 
-- 
2.45.2

[PATCH 21/23] drm/i915/dp: Split AS SDP computation between compute_config and compute_config_late

[Ankit Nautiyal]

Currently we enable AS SDP only when VRR is enabled. As we start using
AS SDP for other features, this becomes a problem. The AS SDP
configuration can change dynamically based on VRR, CMRR, PR, ALPM, etc.
Since these features may be enabled or disabled after the initial
configuration, the AS SDP parameters need to be computed later in the
pipeline.

However, not all of the AS SDP logic can be moved to the late stage:
the VRR guardband optimization depends on knowing early whether AS SDP
can be used. Without this, we would end up accounting for AS SDP on all
platforms that support it, even for panels that do not support AS SDP.
Therefore we set the infoframe enable bit for AS SDP during
compute_config(), before the guardband is computed.

To handle these constraints, split the AS SDP programming into two
phases:

 - intel_dp_compute_as_sdp()
   Runs during compute_config().
   Sets only the infoframe enable bit so that the guardband logic can
   account for AS SDP requirements.

 - intel_dp_as_sdp_compute_config_late()
   Runs during compute_config_late().
   Computes all remaining AS SDP fields based on the features that need
   it.

The late-stage computation is called from
intel_dp_sdp_compute_config_late(), before computing the minimum guardband
for SDPs.

This is a preparatory change. A subsequent patches will compute PR related
AS SDP fields and enable AS SDP not only for VRR but for other features
as well.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 66 ++++++++++++++++---------
 1 file changed, 43 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ddaa187371b8..902c09e0780f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3142,10 +3142,6 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
-	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
-
 	/*
 	 * #FIXME: SDP/infoframe updates aren’t truly atomic, and with the new
 	 * cdclk->tc clock crossing we may transiently send a corrupted packet
@@ -3154,23 +3150,13 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	if (!intel_dp_needs_as_sdp(intel_dp, crtc_state))
 		return;
 
+	/*
+	 * Only set the infoframes.enable flag here. The remaining AS SDP fields
+	 * are programmed in the compute_config_late() phase. We need this flag
+	 * early so that the VRR guardband calculation can properly account for
+	 * AS SDP requirements.
+	 */
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
-
-	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
-	as_sdp->length = 0x9;
-	as_sdp->duration_incr_ms = 0;
-	as_sdp->revision = 0x2;
-	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
-
-	if (crtc_state->cmrr.enable) {
-		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
-		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
-		as_sdp->target_rr_divider = true;
-	} else if (crtc_state->vrr.enable) {
-		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-	} else {
-		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
-	}
 }
 
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
@@ -7371,11 +7357,45 @@ void intel_dp_mst_resume(struct intel_display *display)
 }
 
 static
-int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
+void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *crtc_state)
+{
+	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+
+	if ((crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) == 0)
+		return;
+
+	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+	as_sdp->length = 0x9;
+	as_sdp->duration_incr_ms = 0;
+	as_sdp->revision = 0x2;
+	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
+
+	if (crtc_state->cmrr.enable) {
+		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
+		as_sdp->target_rr_divider = true;
+	} else if (crtc_state->vrr.enable) {
+		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+	}
+}
+
+static
+int intel_dp_sdp_compute_config_late(struct intel_dp *intel_dp,
+				     struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	int guardband = intel_crtc_vblank_length(crtc_state);
-	int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
+	int min_sdp_guardband;
+
+	intel_dp_as_sdp_compute_config_late(intel_dp, crtc_state);
+
+	min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
 
 	if (guardband < min_sdp_guardband) {
 		drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
@@ -7395,7 +7415,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 
 	intel_psr_compute_config_late(intel_dp, crtc_state);
 
-	ret = intel_dp_sdp_compute_config_late(crtc_state);
+	ret = intel_dp_sdp_compute_config_late(intel_dp, crtc_state);
 	if (ret)
 		return ret;
 
-- 
2.45.2

[PATCH 22/23] drm/i915/dp: Compute and include coasting vtotal for AS SDP

[Ankit Nautiyal]

DP v2.1 allows the source to temporarily suspend Adaptive-Sync SDP
transmission while Panel Replay is active when the sink supports
asynchronous video timing.

In such cases, the sink relies on the last transmitted AS SDP timing
information to maintain the refresh rate. To support this behavior,
compute and populate the coasting vtotal field in the AS SDP payload.

Include coasting vtotal in AS SDP packing, unpacking, and comparison,
and set it during late AS SDP configuration for PR with Aux-less ALPM
when asynchronous video timing is supported.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  3 ++-
 drivers/gpu/drm/i915/display/intel_dp.c      | 19 +++++++++++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a0e7ef2574b2..747dd3112d66 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4914,7 +4914,8 @@ intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
 		a->duration_incr_ms == b->duration_incr_ms &&
 		a->duration_decr_ms == b->duration_decr_ms &&
 		a->target_rr_divider == b->target_rr_divider &&
-		a->mode == b->mode;
+		a->mode == b->mode &&
+		a->coasting_vtotal == b->coasting_vtotal;
 }
 
 static bool
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 902c09e0780f..de6f88a5400d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5123,6 +5123,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	if (as_sdp->target_rr_divider)
 		sdp->db[4] |= 0x20;
 
+	sdp->db[7] = as_sdp->coasting_vtotal & 0xFF;
+	sdp->db[8] = (as_sdp->coasting_vtotal >> 8) & 0xFF;
+
 	return length;
 }
 
@@ -5306,6 +5309,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
+	as_sdp->coasting_vtotal = (sdp->db[8] << 8) | sdp->db[7];
 
 	return 0;
 }
@@ -7383,6 +7387,21 @@ void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
 	} else {
 		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
 	}
+
+	/*
+	 * For Panel Replay with Async Video Timing support, the source can
+	 * disable sending the AS SDP during PR Active state. In that case,
+	 * the sink needs the coasting vtotal value to maintain the refresh
+	 * rate.
+	 *
+	 * #TODO:
+	 * If we ever advertise support for coasting at other refresh targets,
+	 * this logic could be revisited. For now, use the minimum refresh rate
+	 * as the only safe coasting value.
+	 */
+	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state) &&
+	    intel_psr_pr_async_video_timing_supported(intel_dp))
+		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
 }
 
 static
-- 
2.45.2

Re: [PATCH 22/23] drm/i915/dp: Compute and include coasting vtotal for AS SDP

[Ville Syrjälä]

On Thu, Apr 02, 2026 at 01:34:22PM +0530, Ankit Nautiyal wrote:
> DP v2.1 allows the source to temporarily suspend Adaptive-Sync SDP
> transmission while Panel Replay is active when the sink supports
> asynchronous video timing.
> 
> In such cases, the sink relies on the last transmitted AS SDP timing
> information to maintain the refresh rate. To support this behavior,
> compute and populate the coasting vtotal field in the AS SDP payload.
> 
> Include coasting vtotal in AS SDP packing, unpacking, and comparison,
> and set it during late AS SDP configuration for PR with Aux-less ALPM
> when asynchronous video timing is supported.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  3 ++-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 19 +++++++++++++++++++
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a0e7ef2574b2..747dd3112d66 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4914,7 +4914,8 @@ intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
>  		a->duration_incr_ms == b->duration_incr_ms &&
>  		a->duration_decr_ms == b->duration_decr_ms &&
>  		a->target_rr_divider == b->target_rr_divider &&
> -		a->mode == b->mode;
> +		a->mode == b->mode &&
> +		a->coasting_vtotal == b->coasting_vtotal;
>  }
>  
>  static bool
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 902c09e0780f..de6f88a5400d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5123,6 +5123,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
>  	if (as_sdp->target_rr_divider)
>  		sdp->db[4] |= 0x20;
>  
> +	sdp->db[7] = as_sdp->coasting_vtotal & 0xFF;
> +	sdp->db[8] = (as_sdp->coasting_vtotal >> 8) & 0xFF;
> +
>  	return length;
>  }
>  
> @@ -5306,6 +5309,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
>  	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
>  	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
>  	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
> +	as_sdp->coasting_vtotal = (sdp->db[8] << 8) | sdp->db[7];
>  
>  	return 0;
>  }
> @@ -7383,6 +7387,21 @@ void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
>  	} else {
>  		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>  	}
> +
> +	/*
> +	 * For Panel Replay with Async Video Timing support, the source can
> +	 * disable sending the AS SDP during PR Active state. In that case,
> +	 * the sink needs the coasting vtotal value to maintain the refresh
> +	 * rate.
> +	 *
> +	 * #TODO:
> +	 * If we ever advertise support for coasting at other refresh targets,
> +	 * this logic could be revisited. For now, use the minimum refresh rate
> +	 * as the only safe coasting value.
> +	 */
> +	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state) &&
> +	    intel_psr_pr_async_video_timing_supported(intel_dp))
> +		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;

Seems reasonable.

Is this always under our control or could the hardware overwrite
this with the current vtotal at the time of PR entry? Assuming
we can enter PR before the vtotal goes back to vmax on its own
anyway.

>  }
>  
>  static
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 22/23] drm/i915/dp: Compute and include coasting vtotal for AS SDP

[Nautiyal, Ankit K]

On 4/2/2026 4:40 PM, Ville Syrjälä wrote:
> On Thu, Apr 02, 2026 at 01:34:22PM +0530, Ankit Nautiyal wrote:
>> DP v2.1 allows the source to temporarily suspend Adaptive-Sync SDP
>> transmission while Panel Replay is active when the sink supports
>> asynchronous video timing.
>>
>> In such cases, the sink relies on the last transmitted AS SDP timing
>> information to maintain the refresh rate. To support this behavior,
>> compute and populate the coasting vtotal field in the AS SDP payload.
>>
>> Include coasting vtotal in AS SDP packing, unpacking, and comparison,
>> and set it during late AS SDP configuration for PR with Aux-less ALPM
>> when asynchronous video timing is supported.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c |  3 ++-
>>   drivers/gpu/drm/i915/display/intel_dp.c      | 19 +++++++++++++++++++
>>   2 files changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index a0e7ef2574b2..747dd3112d66 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -4914,7 +4914,8 @@ intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
>>   		a->duration_incr_ms == b->duration_incr_ms &&
>>   		a->duration_decr_ms == b->duration_decr_ms &&
>>   		a->target_rr_divider == b->target_rr_divider &&
>> -		a->mode == b->mode;
>> +		a->mode == b->mode &&
>> +		a->coasting_vtotal == b->coasting_vtotal;
>>   }
>>   
>>   static bool
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 902c09e0780f..de6f88a5400d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -5123,6 +5123,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
>>   	if (as_sdp->target_rr_divider)
>>   		sdp->db[4] |= 0x20;
>>   
>> +	sdp->db[7] = as_sdp->coasting_vtotal & 0xFF;
>> +	sdp->db[8] = (as_sdp->coasting_vtotal >> 8) & 0xFF;
>> +
>>   	return length;
>>   }
>>   
>> @@ -5306,6 +5309,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
>>   	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
>>   	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
>>   	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
>> +	as_sdp->coasting_vtotal = (sdp->db[8] << 8) | sdp->db[7];
>>   
>>   	return 0;
>>   }
>> @@ -7383,6 +7387,21 @@ void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
>>   	} else {
>>   		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>>   	}
>> +
>> +	/*
>> +	 * For Panel Replay with Async Video Timing support, the source can
>> +	 * disable sending the AS SDP during PR Active state. In that case,
>> +	 * the sink needs the coasting vtotal value to maintain the refresh
>> +	 * rate.
>> +	 *
>> +	 * #TODO:
>> +	 * If we ever advertise support for coasting at other refresh targets,
>> +	 * this logic could be revisited. For now, use the minimum refresh rate
>> +	 * as the only safe coasting value.
>> +	 */
>> +	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state) &&
>> +	    intel_psr_pr_async_video_timing_supported(intel_dp))
>> +		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
> Seems reasonable.
>
> Is this always under our control or could the hardware overwrite
> this with the current vtotal at the time of PR entry? Assuming
> we can enter PR before the vtotal goes back to vmax on its own
> anyway.


What I understand from Bspec in this regard is:

Do not write Adaptive Sync SDP Transmission Disable in PR Active State 
i.e. DB[2], instead use PR_ALPM_CTL[ AS SDP Transmission in Active 
Disable ] bit.

HW will sample the PR_ALPM_CTL bit only when PR is active, and it will 
get reflected in AS SDP payload in an 'appropriate' time.

HW will ignore this bit when PR is Inactive and always send AS SDP.

So I think HW will not touch the coasting vtotal DBs.

Driver should set appropriate coasting Vtotal and set the PR_ALPM_CTL[AS 
SDP Transmission in Active disable] bit.

During PR active Driver will set the DB[2] bit in payload which will 
trigger the sink to use Coasting Vtotal.

(Unless we start writing : DPCD 00B1[0] ie. 
PANEL_REPLAY_CONFIG2[PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED], in 
which sink starts using its own logic).


Regards,

Ankit



>
>>   }
>>   
>>   static
>> -- 
>> 2.45.2

Re: [PATCH 22/23] drm/i915/dp: Compute and include coasting vtotal for AS SDP

[Nautiyal, Ankit K]

On 4/7/2026 4:24 PM, Nautiyal, Ankit K wrote:
>
> On 4/2/2026 4:40 PM, Ville Syrjälä wrote:
>> On Thu, Apr 02, 2026 at 01:34:22PM +0530, Ankit Nautiyal wrote:
>>> DP v2.1 allows the source to temporarily suspend Adaptive-Sync SDP
>>> transmission while Panel Replay is active when the sink supports
>>> asynchronous video timing.
>>>
>>> In such cases, the sink relies on the last transmitted AS SDP timing
>>> information to maintain the refresh rate. To support this behavior,
>>> compute and populate the coasting vtotal field in the AS SDP payload.
>>>
>>> Include coasting vtotal in AS SDP packing, unpacking, and comparison,
>>> and set it during late AS SDP configuration for PR with Aux-less ALPM
>>> when asynchronous video timing is supported.
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_display.c |  3 ++-
>>>   drivers/gpu/drm/i915/display/intel_dp.c      | 19 +++++++++++++++++++
>>>   2 files changed, 21 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>> index a0e7ef2574b2..747dd3112d66 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -4914,7 +4914,8 @@ intel_compare_dp_as_sdp(const struct 
>>> drm_dp_as_sdp *a,
>>>           a->duration_incr_ms == b->duration_incr_ms &&
>>>           a->duration_decr_ms == b->duration_decr_ms &&
>>>           a->target_rr_divider == b->target_rr_divider &&
>>> -        a->mode == b->mode;
>>> +        a->mode == b->mode &&
>>> +        a->coasting_vtotal == b->coasting_vtotal;
>>>   }
>>>     static bool
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 902c09e0780f..de6f88a5400d 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -5123,6 +5123,9 @@ static ssize_t intel_dp_as_sdp_pack(const 
>>> struct drm_dp_as_sdp *as_sdp,
>>>       if (as_sdp->target_rr_divider)
>>>           sdp->db[4] |= 0x20;
>>>   +    sdp->db[7] = as_sdp->coasting_vtotal & 0xFF;
>>> +    sdp->db[8] = (as_sdp->coasting_vtotal >> 8) & 0xFF;
>>> +
>>>       return length;
>>>   }
>>>   @@ -5306,6 +5309,7 @@ int intel_dp_as_sdp_unpack(struct 
>>> drm_dp_as_sdp *as_sdp,
>>>       as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
>>>       as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
>>>       as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
>>> +    as_sdp->coasting_vtotal = (sdp->db[8] << 8) | sdp->db[7];
>>>         return 0;
>>>   }
>>> @@ -7383,6 +7387,21 @@ void 
>>> intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
>>>       } else {
>>>           as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>>>       }
>>> +
>>> +    /*
>>> +     * For Panel Replay with Async Video Timing support, the source 
>>> can
>>> +     * disable sending the AS SDP during PR Active state. In that 
>>> case,
>>> +     * the sink needs the coasting vtotal value to maintain the 
>>> refresh
>>> +     * rate.
>>> +     *
>>> +     * #TODO:
>>> +     * If we ever advertise support for coasting at other refresh 
>>> targets,
>>> +     * this logic could be revisited. For now, use the minimum 
>>> refresh rate
>>> +     * as the only safe coasting value.
>>> +     */
>>> +    if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state) &&
>>> +        intel_psr_pr_async_video_timing_supported(intel_dp))
>>> +        as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
>> Seems reasonable.
>>
>> Is this always under our control or could the hardware overwrite
>> this with the current vtotal at the time of PR entry? Assuming
>> we can enter PR before the vtotal goes back to vmax on its own
>> anyway.
>
>
> What I understand from Bspec in this regard is:
>
> Do not write Adaptive Sync SDP Transmission Disable in PR Active State 
> i.e. DB[2], instead use PR_ALPM_CTL[ AS SDP Transmission in Active 
> Disable ] bit.
>
> HW will sample the PR_ALPM_CTL bit only when PR is active, and it will 
> get reflected in AS SDP payload in an 'appropriate' time.
>
> HW will ignore this bit when PR is Inactive and always send AS SDP.
>
> So I think HW will not touch the coasting vtotal DBs.
>
> Driver should set appropriate coasting Vtotal and set the 
> PR_ALPM_CTL[AS SDP Transmission in Active disable] bit.
>
> During PR active Driver will set the DB[2] bit in payload which will 
> trigger the sink to use Coasting Vtotal.


..HW will set the DB[2] bit ... (facepalm)


>
> (Unless we start writing : DPCD 00B1[0] ie. 
> PANEL_REPLAY_CONFIG2[PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED], 
> in which sink starts using its own logic).
>
>
> Regards,
>
> Ankit
>
>
>
>>
>>>   }
>>>     static
>>> -- 
>>> 2.45.2

Re: [PATCH 22/23] drm/i915/dp: Compute and include coasting vtotal for AS SDP

[Ville Syrjälä]

On Tue, Apr 07, 2026 at 04:26:28PM +0530, Nautiyal, Ankit K wrote:
> 
> On 4/7/2026 4:24 PM, Nautiyal, Ankit K wrote:
> >
> > On 4/2/2026 4:40 PM, Ville Syrjälä wrote:
> >> On Thu, Apr 02, 2026 at 01:34:22PM +0530, Ankit Nautiyal wrote:
> >>> DP v2.1 allows the source to temporarily suspend Adaptive-Sync SDP
> >>> transmission while Panel Replay is active when the sink supports
> >>> asynchronous video timing.
> >>>
> >>> In such cases, the sink relies on the last transmitted AS SDP timing
> >>> information to maintain the refresh rate. To support this behavior,
> >>> compute and populate the coasting vtotal field in the AS SDP payload.
> >>>
> >>> Include coasting vtotal in AS SDP packing, unpacking, and comparison,
> >>> and set it during late AS SDP configuration for PR with Aux-less ALPM
> >>> when asynchronous video timing is supported.
> >>>
> >>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >>> ---
> >>>   drivers/gpu/drm/i915/display/intel_display.c |  3 ++-
> >>>   drivers/gpu/drm/i915/display/intel_dp.c      | 19 +++++++++++++++++++
> >>>   2 files changed, 21 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> >>> b/drivers/gpu/drm/i915/display/intel_display.c
> >>> index a0e7ef2574b2..747dd3112d66 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >>> @@ -4914,7 +4914,8 @@ intel_compare_dp_as_sdp(const struct 
> >>> drm_dp_as_sdp *a,
> >>>           a->duration_incr_ms == b->duration_incr_ms &&
> >>>           a->duration_decr_ms == b->duration_decr_ms &&
> >>>           a->target_rr_divider == b->target_rr_divider &&
> >>> -        a->mode == b->mode;
> >>> +        a->mode == b->mode &&
> >>> +        a->coasting_vtotal == b->coasting_vtotal;
> >>>   }
> >>>     static bool
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> >>> b/drivers/gpu/drm/i915/display/intel_dp.c
> >>> index 902c09e0780f..de6f88a5400d 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >>> @@ -5123,6 +5123,9 @@ static ssize_t intel_dp_as_sdp_pack(const 
> >>> struct drm_dp_as_sdp *as_sdp,
> >>>       if (as_sdp->target_rr_divider)
> >>>           sdp->db[4] |= 0x20;
> >>>   +    sdp->db[7] = as_sdp->coasting_vtotal & 0xFF;
> >>> +    sdp->db[8] = (as_sdp->coasting_vtotal >> 8) & 0xFF;
> >>> +
> >>>       return length;
> >>>   }
> >>>   @@ -5306,6 +5309,7 @@ int intel_dp_as_sdp_unpack(struct 
> >>> drm_dp_as_sdp *as_sdp,
> >>>       as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
> >>>       as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
> >>>       as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
> >>> +    as_sdp->coasting_vtotal = (sdp->db[8] << 8) | sdp->db[7];
> >>>         return 0;
> >>>   }
> >>> @@ -7383,6 +7387,21 @@ void 
> >>> intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
> >>>       } else {
> >>>           as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
> >>>       }
> >>> +
> >>> +    /*
> >>> +     * For Panel Replay with Async Video Timing support, the source 
> >>> can
> >>> +     * disable sending the AS SDP during PR Active state. In that 
> >>> case,
> >>> +     * the sink needs the coasting vtotal value to maintain the 
> >>> refresh
> >>> +     * rate.
> >>> +     *
> >>> +     * #TODO:
> >>> +     * If we ever advertise support for coasting at other refresh 
> >>> targets,
> >>> +     * this logic could be revisited. For now, use the minimum 
> >>> refresh rate
> >>> +     * as the only safe coasting value.
> >>> +     */
> >>> +    if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state) &&
> >>> +        intel_psr_pr_async_video_timing_supported(intel_dp))
> >>> +        as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
> >> Seems reasonable.
> >>
> >> Is this always under our control or could the hardware overwrite
> >> this with the current vtotal at the time of PR entry? Assuming
> >> we can enter PR before the vtotal goes back to vmax on its own
> >> anyway.
> >
> >
> > What I understand from Bspec in this regard is:
> >
> > Do not write Adaptive Sync SDP Transmission Disable in PR Active State 
> > i.e. DB[2], instead use PR_ALPM_CTL[ AS SDP Transmission in Active 
> > Disable ] bit.
> >
> > HW will sample the PR_ALPM_CTL bit only when PR is active, and it will 
> > get reflected in AS SDP payload in an 'appropriate' time.
> >
> > HW will ignore this bit when PR is Inactive and always send AS SDP.
> >
> > So I think HW will not touch the coasting vtotal DBs.
> >
> > Driver should set appropriate coasting Vtotal and set the 
> > PR_ALPM_CTL[AS SDP Transmission in Active disable] bit.
> >
> > During PR active Driver will set the DB[2] bit in payload which will 
> > trigger the sink to use Coasting Vtotal.
> 
> 
> ..HW will set the DB[2] bit ... (facepalm)

OK. Might be good to note in the commit message that this fully
under driver control. I suppose it would be good to make that
statement (one way or the other) for any additions we do to the
AS SDP payload...

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> 
> >
> > (Unless we start writing : DPCD 00B1[0] ie. 
> > PANEL_REPLAY_CONFIG2[PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED], 
> > in which sink starts using its own logic).
> >
> >
> > Regards,
> >
> > Ankit
> >
> >
> >
> >>
> >>>   }
> >>>     static
> >>> -- 
> >>> 2.45.2

-- 
Ville Syrjälä
Intel

[PATCH 23/23] drm/i915/dp: Always enable AS SDP if supported by source + sink

[Ankit Nautiyal]

Currently AS SDP is only configured when VRR is enabled. However, other
use cases like CMRR, Panel Replay, etc. also send information to the sink
via AS SDPs.

With optimized guardband, we also need to account for wakeup time and other
relevant details that depend on the AS SDP position whenever AS SDP is
enabled. If a feature enabling AS SDP gets turned on later (after modeset),
the guardband might not be sufficient and may need to increase, triggering
a full modeset.

To avoid this, always send AS SDP whenever:
 - the source and sink both support it, AND,
 - there is a possibility to use it for VRR and Panel Replay for
   synchronization.

v2: Check if AS SDP can be used for synchronization for VRR or PR. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f5d96074c48e..5fc545d95cae 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3136,7 +3136,11 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	if (drm_dp_is_branch(intel_dp->dpcd))
 		return false;
 
-	return crtc_state->vrr.enable;
+	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state) &&
+	    !intel_psr_pr_async_video_timing_supported(intel_dp))
+		return true;
+
+	return intel_vrr_possible(crtc_state);
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-- 
2.45.2