[PATCH 0/7] accel/ivpu fixes for 6.8-rc3

[PATCH 0/7] accel/ivpu fixes for 6.8-rc3

[Jacek Lawrynowicz]

A couple of small patches focused on improving driver stability.
In addition d3hot_delay patch improves LNL inference latency.

Grzegorz Trzebiatowski (1):
  accel/ivpu: Add job status for jobs aborted by the driver

Jacek Lawrynowicz (1):
  accel/ivpu: Disable d3hot_delay on all NPU generations

Krystian Pradzynski (2):
  accel/ivpu/40xx: Enable D0i3 message
  accel/ivpu/40xx: Stop passing SKU boot parameters to FW

Wachowski, Karol (3):
  accel/ivpu: Force snooping for MMU writes
  accel/ivpu: Correct MMU queue size checking functions
  accel/ivpu: Gracefully shutdown NPU before reset

 drivers/accel/ivpu/ivpu_drv.c     |   5 +-
 drivers/accel/ivpu/ivpu_fw.c      |   1 -
 drivers/accel/ivpu/ivpu_hw_37xx.c | 124 +++++++++++++++---------------
 drivers/accel/ivpu/ivpu_hw_40xx.c |   7 +-
 drivers/accel/ivpu/ivpu_job.c     |   4 +-
 drivers/accel/ivpu/ivpu_mmu.c     |  36 +++++----
 include/uapi/drm/ivpu_accel.h     |   1 +
 7 files changed, 89 insertions(+), 89 deletions(-)

--
2.43.0

[PATCH 1/7] accel/ivpu: Force snooping for MMU writes

[Jacek Lawrynowicz]

From: "Wachowski, Karol" <karol.wachowski@intel.com>

Set AW_SNOOP_OVERRIDE bit in VPU_37/40XX_HOST_IF_TCU_PTW_OVERRIDES
to force snooping for MMU write accesses (setting event queue events).

MMU event queue buffer is the only buffer written by MMU and
mapped as write-back which break cache coherency. Force write
transactions to be snooped solving the problem.

Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_hw_37xx.c | 2 +-
 drivers/accel/ivpu/ivpu_hw_40xx.c | 2 +-
 drivers/accel/ivpu/ivpu_mmu.c     | 3 ---
 3 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_hw_37xx.c b/drivers/accel/ivpu/ivpu_hw_37xx.c
index f15a93d83057..77accd029c4a 100644
--- a/drivers/accel/ivpu/ivpu_hw_37xx.c
+++ b/drivers/accel/ivpu/ivpu_hw_37xx.c
@@ -525,7 +525,7 @@ static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
 	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
 
 	val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val);
-	val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);
+	val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);
 	val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);
 
 	REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val);
diff --git a/drivers/accel/ivpu/ivpu_hw_40xx.c b/drivers/accel/ivpu/ivpu_hw_40xx.c
index 704288084f37..86b89b94f9f3 100644
--- a/drivers/accel/ivpu/ivpu_hw_40xx.c
+++ b/drivers/accel/ivpu/ivpu_hw_40xx.c
@@ -530,7 +530,7 @@ static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
 	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);
 
 	val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);
-	val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);
+	val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);
 	val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
 
 	REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);
diff --git a/drivers/accel/ivpu/ivpu_mmu.c b/drivers/accel/ivpu/ivpu_mmu.c
index 9a3122ffce03..8df78adeee33 100644
--- a/drivers/accel/ivpu/ivpu_mmu.c
+++ b/drivers/accel/ivpu/ivpu_mmu.c
@@ -560,7 +560,6 @@ static int ivpu_mmu_reset(struct ivpu_device *vdev)
 	mmu->cmdq.cons = 0;
 
 	memset(mmu->evtq.base, 0, IVPU_MMU_EVTQ_SIZE);
-	clflush_cache_range(mmu->evtq.base, IVPU_MMU_EVTQ_SIZE);
 	mmu->evtq.prod = 0;
 	mmu->evtq.cons = 0;
 
@@ -877,8 +876,6 @@ static u32 *ivpu_mmu_get_event(struct ivpu_device *vdev)
 	if (!CIRC_CNT(IVPU_MMU_Q_IDX(evtq->prod), IVPU_MMU_Q_IDX(evtq->cons), IVPU_MMU_Q_COUNT))
 		return NULL;
 
-	clflush_cache_range(evt, IVPU_MMU_EVTQ_CMD_SIZE);
-
 	evtq->cons = (evtq->cons + 1) & IVPU_MMU_Q_WRAP_MASK;
 	REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, evtq->cons);
 
-- 
2.43.0

[PATCH 2/7] accel/ivpu: Correct MMU queue size checking functions

[Jacek Lawrynowicz]

From: "Wachowski, Karol" <karol.wachowski@intel.com>

Do not use kernel CIRC_SPACE and CIRC_CNT that
incorrectly return space of a queue when wrap bit was set.
Use correct implementation that compares producer, consumer and
wrap bit values.

Without this fix it was possible to lose events in case when event
queue was full.

Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_mmu.c | 33 ++++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_mmu.c b/drivers/accel/ivpu/ivpu_mmu.c
index 8df78adeee33..91bd640655ab 100644
--- a/drivers/accel/ivpu/ivpu_mmu.c
+++ b/drivers/accel/ivpu/ivpu_mmu.c
@@ -72,10 +72,10 @@
 
 #define IVPU_MMU_Q_COUNT_LOG2		4 /* 16 entries */
 #define IVPU_MMU_Q_COUNT		((u32)1 << IVPU_MMU_Q_COUNT_LOG2)
-#define IVPU_MMU_Q_WRAP_BIT		(IVPU_MMU_Q_COUNT << 1)
-#define IVPU_MMU_Q_WRAP_MASK		(IVPU_MMU_Q_WRAP_BIT - 1)
-#define IVPU_MMU_Q_IDX_MASK		(IVPU_MMU_Q_COUNT - 1)
+#define IVPU_MMU_Q_WRAP_MASK            GENMASK(IVPU_MMU_Q_COUNT_LOG2, 0)
+#define IVPU_MMU_Q_IDX_MASK             (IVPU_MMU_Q_COUNT - 1)
 #define IVPU_MMU_Q_IDX(val)		((val) & IVPU_MMU_Q_IDX_MASK)
+#define IVPU_MMU_Q_WRP(val)             ((val) & IVPU_MMU_Q_COUNT)
 
 #define IVPU_MMU_CMDQ_CMD_SIZE		16
 #define IVPU_MMU_CMDQ_SIZE		(IVPU_MMU_Q_COUNT * IVPU_MMU_CMDQ_CMD_SIZE)
@@ -475,20 +475,32 @@ static int ivpu_mmu_cmdq_wait_for_cons(struct ivpu_device *vdev)
 	return 0;
 }
 
+static bool ivpu_mmu_queue_is_full(struct ivpu_mmu_queue *q)
+{
+	return ((IVPU_MMU_Q_IDX(q->prod) == IVPU_MMU_Q_IDX(q->cons)) &&
+		(IVPU_MMU_Q_WRP(q->prod) != IVPU_MMU_Q_WRP(q->cons)));
+}
+
+static bool ivpu_mmu_queue_is_empty(struct ivpu_mmu_queue *q)
+{
+	return ((IVPU_MMU_Q_IDX(q->prod) == IVPU_MMU_Q_IDX(q->cons)) &&
+		(IVPU_MMU_Q_WRP(q->prod) == IVPU_MMU_Q_WRP(q->cons)));
+}
+
 static int ivpu_mmu_cmdq_cmd_write(struct ivpu_device *vdev, const char *name, u64 data0, u64 data1)
 {
-	struct ivpu_mmu_queue *q = &vdev->mmu->cmdq;
-	u64 *queue_buffer = q->base;
-	int idx = IVPU_MMU_Q_IDX(q->prod) * (IVPU_MMU_CMDQ_CMD_SIZE / sizeof(*queue_buffer));
+	struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq;
+	u64 *queue_buffer = cmdq->base;
+	int idx = IVPU_MMU_Q_IDX(cmdq->prod) * (IVPU_MMU_CMDQ_CMD_SIZE / sizeof(*queue_buffer));
 
-	if (!CIRC_SPACE(IVPU_MMU_Q_IDX(q->prod), IVPU_MMU_Q_IDX(q->cons), IVPU_MMU_Q_COUNT)) {
+	if (ivpu_mmu_queue_is_full(cmdq)) {
 		ivpu_err(vdev, "Failed to write MMU CMD %s\n", name);
 		return -EBUSY;
 	}
 
 	queue_buffer[idx] = data0;
 	queue_buffer[idx + 1] = data1;
-	q->prod = (q->prod + 1) & IVPU_MMU_Q_WRAP_MASK;
+	cmdq->prod = (cmdq->prod + 1) & IVPU_MMU_Q_WRAP_MASK;
 
 	ivpu_dbg(vdev, MMU, "CMD write: %s data: 0x%llx 0x%llx\n", name, data0, data1);
 
@@ -873,12 +885,10 @@ static u32 *ivpu_mmu_get_event(struct ivpu_device *vdev)
 	u32 *evt = evtq->base + (idx * IVPU_MMU_EVTQ_CMD_SIZE);
 
 	evtq->prod = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC);
-	if (!CIRC_CNT(IVPU_MMU_Q_IDX(evtq->prod), IVPU_MMU_Q_IDX(evtq->cons), IVPU_MMU_Q_COUNT))
+	if (ivpu_mmu_queue_is_empty(evtq))
 		return NULL;
 
 	evtq->cons = (evtq->cons + 1) & IVPU_MMU_Q_WRAP_MASK;
-	REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, evtq->cons);
-
 	return evt;
 }
 
@@ -899,6 +909,7 @@ void ivpu_mmu_irq_evtq_handler(struct ivpu_device *vdev)
 		}
 
 		ivpu_mmu_user_context_mark_invalid(vdev, ssid);
+		REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, vdev->mmu->evtq.cons);
 	}
 }
 
-- 
2.43.0

[PATCH 3/7] accel/ivpu: Disable d3hot_delay on all NPU generations

[Jacek Lawrynowicz]

NPU does not require this delay regardless of the generation.
All generations are integrated into the SOC.

Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_drv.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c
index 9418c73ee8ef..4b0640226986 100644
--- a/drivers/accel/ivpu/ivpu_drv.c
+++ b/drivers/accel/ivpu/ivpu_drv.c
@@ -480,9 +480,8 @@ static int ivpu_pci_init(struct ivpu_device *vdev)
 	/* Clear any pending errors */
 	pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f);
 
-	/* VPU 37XX does not require 10m D3hot delay */
-	if (ivpu_hw_gen(vdev) == IVPU_HW_37XX)
-		pdev->d3hot_delay = 0;
+	/* NPU does not require 10m D3hot delay */
+	pdev->d3hot_delay = 0;
 
 	ret = pcim_enable_device(pdev);
 	if (ret) {
-- 
2.43.0

[PATCH 4/7] accel/ivpu: Gracefully shutdown NPU before reset

[Jacek Lawrynowicz]

From: "Wachowski, Karol" <karol.wachowski@intel.com>

Replace forceful disable of power domains with requests to disable
TOP NOC CPU_CTRL and HOSTIF_L2CACHE through QREQN.

In case of failure retry multiple times following HAS sequence of
checking both QACCEPN and QDENYN registers.

This fixes VPU hangs with PCODE released in January 2024 onwards.

Fixes: 3f7c0634926d ("accel/ivpu/37xx: Fix hangs related to MMIO reset")
Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_hw_37xx.c | 122 +++++++++++++++---------------
 1 file changed, 60 insertions(+), 62 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_hw_37xx.c b/drivers/accel/ivpu/ivpu_hw_37xx.c
index 77accd029c4a..b1a3a19c8986 100644
--- a/drivers/accel/ivpu/ivpu_hw_37xx.c
+++ b/drivers/accel/ivpu/ivpu_hw_37xx.c
@@ -332,28 +332,6 @@ static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
 	return 0;
 }
 
-static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
-{
-	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN);
-
-	if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
-	    !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
-		return -EIO;
-
-	return 0;
-}
-
-static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
-{
-	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY);
-
-	if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
-	    !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
-		return -EIO;
-
-	return 0;
-}
-
 static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev)
 {
 	ivpu_boot_host_ss_rst_clr_assert(vdev);
@@ -396,37 +374,68 @@ static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
 	return ivpu_boot_host_ss_axi_drive(vdev, true);
 }
 
-static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
+static int ivpu_boot_host_ss_top_noc_qacceptn_check(struct ivpu_device *vdev, bool enable, u32 mask)
+{
+	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN) & mask;
+
+	if (enable && val == mask)
+		return 0;
+
+	if (!enable && val == 0)
+		return 0;
+
+	ivpu_dbg(vdev, PM, "Failed qacceptn check 0x%x (mask 0x%x enable %d)\n", val, mask, enable);
+	return -EIO;
+}
+
+static int ivpu_boot_host_ss_top_noc_qdeny_check(struct ivpu_device *vdev, u32 mask)
+{
+	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY) & mask;
+
+	if (val) {
+		ivpu_dbg(vdev, PM, "Failed qdeny check 0x%x (mask 0x%x)\n", val, mask);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable, u32 mask)
 {
-	int ret;
 	u32 val;
 
 	val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
-	if (enable) {
-		val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
-		val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
-	} else {
-		val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
-		val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
-	}
-	REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val);
+	if (enable)
+		REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val | mask);
+	else
+		REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val & ~mask);
 
-	ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
-	if (ret) {
-		ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
-		return ret;
-	}
+	if (!ivpu_boot_host_ss_top_noc_qacceptn_check(vdev, enable, mask))
+		return 0;
 
-	ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
-	if (ret)
-		ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
+	if (!enable && ivpu_boot_host_ss_top_noc_qdeny_check(vdev, mask))
+		REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val | mask);
 
-	return ret;
+	return -EIO;
 }
 
 static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
 {
-	return ivpu_boot_host_ss_top_noc_drive(vdev, true);
+	return ivpu_boot_host_ss_top_noc_drive(vdev, true,
+					       VPU_37XX_TOP_NOC_QREQN_CPU_CTRL_MASK |
+					       VPU_37XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK);
+}
+
+static int ivpu_boot_host_ss_top_noc_cpu_ctrl_disable(struct ivpu_device *vdev)
+{
+	return ivpu_boot_host_ss_top_noc_drive(vdev, false,
+					       VPU_37XX_TOP_NOC_QREQN_CPU_CTRL_MASK);
+}
+
+static int ivpu_boot_host_ss_top_noc_hostif_l2cache_disable(struct ivpu_device *vdev)
+{
+	return ivpu_boot_host_ss_top_noc_drive(vdev, false,
+					       VPU_37XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK);
 }
 
 static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
@@ -510,16 +519,6 @@ static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
 	return ret;
 }
 
-static int ivpu_boot_pwr_domain_disable(struct ivpu_device *vdev)
-{
-	ivpu_boot_dpu_active_drive(vdev, false);
-	ivpu_boot_pwr_island_isolation_drive(vdev, true);
-	ivpu_boot_pwr_island_trickle_drive(vdev, false);
-	ivpu_boot_pwr_island_drive(vdev, false);
-
-	return ivpu_boot_wait_for_pwr_island_status(vdev, 0x0);
-}
-
 static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
 {
 	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
@@ -618,19 +617,18 @@ static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev)
 
 static int ivpu_hw_37xx_reset(struct ivpu_device *vdev)
 {
-	int ret = 0;
+	int retries = 100;
 
-	if (ivpu_boot_pwr_domain_disable(vdev)) {
-		ivpu_err(vdev, "Failed to disable power domain\n");
-		ret = -EIO;
-	}
+	while (ivpu_boot_host_ss_top_noc_cpu_ctrl_disable(vdev) && --retries > 0)
+		ivpu_warn(vdev, "Retrying to disable CPU control, retries left: %d\n", retries);
 
-	if (ivpu_pll_disable(vdev)) {
-		ivpu_err(vdev, "Failed to disable PLL\n");
-		ret = -EIO;
-	}
+	while (ivpu_boot_host_ss_top_noc_hostif_l2cache_disable(vdev) && --retries > 0)
+		ivpu_warn(vdev, "Retrying to disable HostIf L2 Cache, retries left: %d\n", retries);
 
-	return ret;
+	while (ivpu_pll_disable(vdev) && --retries > 0)
+		ivpu_warn(vdev, "Retrying to disable PLL, retries left: %d\n", retries);
+
+	return retries > 0 ? 0 : -EIO;
 }
 
 static int ivpu_hw_37xx_d0i3_enable(struct ivpu_device *vdev)
-- 
2.43.0

[PATCH 5/7] accel/ivpu/40xx: Enable D0i3 message

[Jacek Lawrynowicz]

From: Krystian Pradzynski <krystian.pradzynski@intel.com>

All recent 40xx firmware already supports D0i3 entry message and this
WA is no longer needed.

Signed-off-by: Krystian Pradzynski <krystian.pradzynski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_fw.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c
index 6576232f3e67..5fa8bd4603d5 100644
--- a/drivers/accel/ivpu/ivpu_fw.c
+++ b/drivers/accel/ivpu/ivpu_fw.c
@@ -222,7 +222,6 @@ ivpu_fw_init_wa(struct ivpu_device *vdev)
 	const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data;
 
 	if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) ||
-	    (ivpu_hw_gen(vdev) > IVPU_HW_37XX) ||
 	    (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE))
 		vdev->wa.disable_d0i3_msg = true;
 
-- 
2.43.0

[PATCH 6/7] accel/ivpu/40xx: Stop passing SKU boot parameters to FW

[Jacek Lawrynowicz]

From: Krystian Pradzynski <krystian.pradzynski@intel.com>

This parameter was never used by the 40xx FW.

Signed-off-by: Krystian Pradzynski <krystian.pradzynski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_hw_40xx.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_hw_40xx.c b/drivers/accel/ivpu/ivpu_hw_40xx.c
index 86b89b94f9f3..1c995307c113 100644
--- a/drivers/accel/ivpu/ivpu_hw_40xx.c
+++ b/drivers/accel/ivpu/ivpu_hw_40xx.c
@@ -704,7 +704,6 @@ static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev)
 {
 	struct ivpu_hw_info *hw = vdev->hw;
 	u32 tile_disable;
-	u32 tile_enable;
 	u32 fuse;
 
 	fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE);
@@ -725,10 +724,6 @@ static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev)
 	else
 		ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", TILE_MAX_NUM);
 
-	tile_enable = (~tile_disable) & TILE_MAX_MASK;
-
-	hw->sku = REG_SET_FLD_NUM(SKU, HW_ID, LNL_HW_ID, hw->sku);
-	hw->sku = REG_SET_FLD_NUM(SKU, TILE, tile_enable, hw->sku);
 	hw->tile_fuse = tile_disable;
 	hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
 
-- 
2.43.0

[PATCH 7/7] accel/ivpu: Add job status for jobs aborted by the driver

[Jacek Lawrynowicz]

From: Grzegorz Trzebiatowski <grzegorz.trzebiatowski@intel.com>

Add DRM_IVPU_JOB_STATUS_ABORTED to indicate that the job was aborted
by the driver due to e.g. TDR or user context MMU faults.

This will help UMD and tests distinguish if job was aborted by the FW
or the driver.

Signed-off-by: Grzegorz Trzebiatowski <grzegorz.trzebiatowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_job.c | 4 ++--
 include/uapi/drm/ivpu_accel.h | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_job.c b/drivers/accel/ivpu/ivpu_job.c
index 0440bee3ecaf..e70cfb859339 100644
--- a/drivers/accel/ivpu/ivpu_job.c
+++ b/drivers/accel/ivpu/ivpu_job.c
@@ -294,7 +294,7 @@ static int ivpu_job_signal_and_destroy(struct ivpu_device *vdev, u32 job_id, u32
 		return -ENOENT;
 
 	if (job->file_priv->has_mmu_faults)
-		job_status = VPU_JSM_STATUS_ABORTED;
+		job_status = DRM_IVPU_JOB_STATUS_ABORTED;
 
 	job->bos[CMD_BUF_IDX]->job_status = job_status;
 	dma_fence_signal(job->done_fence);
@@ -315,7 +315,7 @@ void ivpu_jobs_abort_all(struct ivpu_device *vdev)
 	unsigned long id;
 
 	xa_for_each(&vdev->submitted_jobs_xa, id, job)
-		ivpu_job_signal_and_destroy(vdev, id, VPU_JSM_STATUS_ABORTED);
+		ivpu_job_signal_and_destroy(vdev, id, DRM_IVPU_JOB_STATUS_ABORTED);
 }
 
 static int ivpu_job_submit(struct ivpu_job *job)
diff --git a/include/uapi/drm/ivpu_accel.h b/include/uapi/drm/ivpu_accel.h
index 63c49318a863..19a13468eca5 100644
--- a/include/uapi/drm/ivpu_accel.h
+++ b/include/uapi/drm/ivpu_accel.h
@@ -305,6 +305,7 @@ struct drm_ivpu_submit {
 
 /* drm_ivpu_bo_wait job status codes */
 #define DRM_IVPU_JOB_STATUS_SUCCESS 0
+#define DRM_IVPU_JOB_STATUS_ABORTED 256
 
 /**
  * struct drm_ivpu_bo_wait - Wait for BO to become inactive
-- 
2.43.0

Re: [PATCH 1/7] accel/ivpu: Force snooping for MMU writes

[Jeffrey Hugo]

On 1/26/2024 5:27 AM, Jacek Lawrynowicz wrote:
> From: "Wachowski, Karol" <karol.wachowski@intel.com>
> 
> Set AW_SNOOP_OVERRIDE bit in VPU_37/40XX_HOST_IF_TCU_PTW_OVERRIDES
> to force snooping for MMU write accesses (setting event queue events).
> 
> MMU event queue buffer is the only buffer written by MMU and
> mapped as write-back which break cache coherency. Force write
> transactions to be snooped solving the problem.
> 
> Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>

Re: [PATCH 2/7] accel/ivpu: Correct MMU queue size checking functions

[Jeffrey Hugo]

On 1/26/2024 5:27 AM, Jacek Lawrynowicz wrote:
> From: "Wachowski, Karol" <karol.wachowski@intel.com>
> 
> Do not use kernel CIRC_SPACE and CIRC_CNT that
> incorrectly return space of a queue when wrap bit was set.
> Use correct implementation that compares producer, consumer and
> wrap bit values.
> 
> Without this fix it was possible to lose events in case when event
> queue was full.
> 
> Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>

Re: [PATCH 3/7] accel/ivpu: Disable d3hot_delay on all NPU generations

[Jeffrey Hugo]

On 1/26/2024 5:28 AM, Jacek Lawrynowicz wrote:
> NPU does not require this delay regardless of the generation.
> All generations are integrated into the SOC.
> 
> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>

Re: [PATCH 4/7] accel/ivpu: Gracefully shutdown NPU before reset

[Jeffrey Hugo]

On 1/26/2024 5:28 AM, Jacek Lawrynowicz wrote:
> From: "Wachowski, Karol" <karol.wachowski@intel.com>
> 
> Replace forceful disable of power domains with requests to disable
> TOP NOC CPU_CTRL and HOSTIF_L2CACHE through QREQN.
> 
> In case of failure retry multiple times following HAS sequence of
> checking both QACCEPN and QDENYN registers.
> 
> This fixes VPU hangs with PCODE released in January 2024 onwards.
> 
> Fixes: 3f7c0634926d ("accel/ivpu/37xx: Fix hangs related to MMIO reset")
> Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
> ---
>   drivers/accel/ivpu/ivpu_hw_37xx.c | 122 +++++++++++++++---------------
>   1 file changed, 60 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/accel/ivpu/ivpu_hw_37xx.c b/drivers/accel/ivpu/ivpu_hw_37xx.c
> index 77accd029c4a..b1a3a19c8986 100644
> --- a/drivers/accel/ivpu/ivpu_hw_37xx.c
> +++ b/drivers/accel/ivpu/ivpu_hw_37xx.c
> @@ -332,28 +332,6 @@ static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
>   	return 0;
>   }
>   
> -static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
> -{
> -	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN);
> -
> -	if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
> -	    !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
> -		return -EIO;
> -
> -	return 0;
> -}
> -
> -static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
> -{
> -	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY);
> -
> -	if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
> -	    !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
> -		return -EIO;
> -
> -	return 0;
> -}
> -
>   static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev)
>   {
>   	ivpu_boot_host_ss_rst_clr_assert(vdev);
> @@ -396,37 +374,68 @@ static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
>   	return ivpu_boot_host_ss_axi_drive(vdev, true);
>   }
>   
> -static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
> +static int ivpu_boot_host_ss_top_noc_qacceptn_check(struct ivpu_device *vdev, bool enable, u32 mask)
> +{
> +	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN) & mask;
> +
> +	if (enable && val == mask)
> +		return 0;
> +
> +	if (!enable && val == 0)
> +		return 0;
> +
> +	ivpu_dbg(vdev, PM, "Failed qacceptn check 0x%x (mask 0x%x enable %d)\n", val, mask, enable);
> +	return -EIO;
> +}
> +
> +static int ivpu_boot_host_ss_top_noc_qdeny_check(struct ivpu_device *vdev, u32 mask)
> +{
> +	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY) & mask;
> +
> +	if (val) {
> +		ivpu_dbg(vdev, PM, "Failed qdeny check 0x%x (mask 0x%x)\n", val, mask);
> +		return -EIO;
> +	}
> +
> +	return 0;
> +}
> +
> +static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable, u32 mask)
>   {
> -	int ret;
>   	u32 val;
>   
>   	val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
> -	if (enable) {
> -		val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
> -		val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
> -	} else {
> -		val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
> -		val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
> -	}
> -	REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val);
> +	if (enable)
> +		REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val | mask);
> +	else
> +		REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val & ~mask);
>   
> -	ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
> -	if (ret) {
> -		ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
> -		return ret;
> -	}
> +	if (!ivpu_boot_host_ss_top_noc_qacceptn_check(vdev, enable, mask))
> +		return 0;
>   
> -	ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
> -	if (ret)
> -		ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
> +	if (!enable && ivpu_boot_host_ss_top_noc_qdeny_check(vdev, mask))
> +		REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val | mask);
>   
> -	return ret;
> +	return -EIO;
>   }
>   
>   static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
>   {
> -	return ivpu_boot_host_ss_top_noc_drive(vdev, true);
> +	return ivpu_boot_host_ss_top_noc_drive(vdev, true,
> +					       VPU_37XX_TOP_NOC_QREQN_CPU_CTRL_MASK |
> +					       VPU_37XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK);
> +}
> +
> +static int ivpu_boot_host_ss_top_noc_cpu_ctrl_disable(struct ivpu_device *vdev)
> +{
> +	return ivpu_boot_host_ss_top_noc_drive(vdev, false,
> +					       VPU_37XX_TOP_NOC_QREQN_CPU_CTRL_MASK);
> +}
> +
> +static int ivpu_boot_host_ss_top_noc_hostif_l2cache_disable(struct ivpu_device *vdev)
> +{
> +	return ivpu_boot_host_ss_top_noc_drive(vdev, false,
> +					       VPU_37XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK);
>   }
>   
>   static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
> @@ -510,16 +519,6 @@ static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
>   	return ret;
>   }
>   
> -static int ivpu_boot_pwr_domain_disable(struct ivpu_device *vdev)
> -{
> -	ivpu_boot_dpu_active_drive(vdev, false);
> -	ivpu_boot_pwr_island_isolation_drive(vdev, true);
> -	ivpu_boot_pwr_island_trickle_drive(vdev, false);
> -	ivpu_boot_pwr_island_drive(vdev, false);
> -
> -	return ivpu_boot_wait_for_pwr_island_status(vdev, 0x0);
> -}
> -
>   static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
>   {
>   	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
> @@ -618,19 +617,18 @@ static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev)
>   
>   static int ivpu_hw_37xx_reset(struct ivpu_device *vdev)
>   {
> -	int ret = 0;
> +	int retries = 100;
>   
> -	if (ivpu_boot_pwr_domain_disable(vdev)) {
> -		ivpu_err(vdev, "Failed to disable power domain\n");
> -		ret = -EIO;
> -	}
> +	while (ivpu_boot_host_ss_top_noc_cpu_ctrl_disable(vdev) && --retries > 0)
> +		ivpu_warn(vdev, "Retrying to disable CPU control, retries left: %d\n", retries);
>   
> -	if (ivpu_pll_disable(vdev)) {
> -		ivpu_err(vdev, "Failed to disable PLL\n");
> -		ret = -EIO;
> -	}
> +	while (ivpu_boot_host_ss_top_noc_hostif_l2cache_disable(vdev) && --retries > 0)
> +		ivpu_warn(vdev, "Retrying to disable HostIf L2 Cache, retries left: %d\n", retries);
>   
> -	return ret;
> +	while (ivpu_pll_disable(vdev) && --retries > 0)
> +		ivpu_warn(vdev, "Retrying to disable PLL, retries left: %d\n", retries);
> +
> +	return retries > 0 ? 0 : -EIO;

It seems weird that retries is never reset between operations.  Why is that?

Re: [PATCH 5/7] accel/ivpu/40xx: Enable D0i3 message

[Jeffrey Hugo]

On 1/26/2024 5:28 AM, Jacek Lawrynowicz wrote:
> From: Krystian Pradzynski <krystian.pradzynski@intel.com>
> 
> All recent 40xx firmware already supports D0i3 entry message and this
> WA is no longer needed.

Can I assume that the workaround only applies to pre-production firmware?

Re: [PATCH 6/7] accel/ivpu/40xx: Stop passing SKU boot parameters to FW

[Jeffrey Hugo]

On 1/26/2024 5:28 AM, Jacek Lawrynowicz wrote:
> From: Krystian Pradzynski <krystian.pradzynski@intel.com>
> 
> This parameter was never used by the 40xx FW.
> 
> Signed-off-by: Krystian Pradzynski <krystian.pradzynski@intel.com>
> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>

Re: [PATCH 7/7] accel/ivpu: Add job status for jobs aborted by the driver

[Jeffrey Hugo]

On 1/26/2024 5:28 AM, Jacek Lawrynowicz wrote:
> From: Grzegorz Trzebiatowski <grzegorz.trzebiatowski@intel.com>
> 
> Add DRM_IVPU_JOB_STATUS_ABORTED to indicate that the job was aborted
> by the driver due to e.g. TDR or user context MMU faults.
> 
> This will help UMD and tests distinguish if job was aborted by the FW
> or the driver.
> 
> Signed-off-by: Grzegorz Trzebiatowski <grzegorz.trzebiatowski@intel.com>
> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>

Re: [PATCH 5/7] accel/ivpu/40xx: Enable D0i3 message

[Jacek Lawrynowicz]

On 26.01.2024 19:24, Jeffrey Hugo wrote:
> On 1/26/2024 5:28 AM, Jacek Lawrynowicz wrote:
>> From: Krystian Pradzynski <krystian.pradzynski@intel.com>
>>
>> All recent 40xx firmware already supports D0i3 entry message and this
>> WA is no longer needed.
> 
> Can I assume that the workaround only applies to pre-production firmware?
Yes, this was only affecting very early versions of the FW.

Re: [PATCH 4/7] accel/ivpu: Gracefully shutdown NPU before reset

[Jacek Lawrynowicz]

On 26.01.2024 19:23, Jeffrey Hugo wrote:
> On 1/26/2024 5:28 AM, Jacek Lawrynowicz wrote:
>> From: "Wachowski, Karol" <karol.wachowski@intel.com>
>>
>> Replace forceful disable of power domains with requests to disable
>> TOP NOC CPU_CTRL and HOSTIF_L2CACHE through QREQN.
>>
>> In case of failure retry multiple times following HAS sequence of
>> checking both QACCEPN and QDENYN registers.
>>
>> This fixes VPU hangs with PCODE released in January 2024 onwards.
>>
>> Fixes: 3f7c0634926d ("accel/ivpu/37xx: Fix hangs related to MMIO reset")
>> Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
>> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
>> ---
>>   drivers/accel/ivpu/ivpu_hw_37xx.c | 122 +++++++++++++++---------------
>>   1 file changed, 60 insertions(+), 62 deletions(-)
>>
>> diff --git a/drivers/accel/ivpu/ivpu_hw_37xx.c b/drivers/accel/ivpu/ivpu_hw_37xx.c
>> index 77accd029c4a..b1a3a19c8986 100644
>> --- a/drivers/accel/ivpu/ivpu_hw_37xx.c
>> +++ b/drivers/accel/ivpu/ivpu_hw_37xx.c
>> @@ -332,28 +332,6 @@ static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
>>       return 0;
>>   }
>>   -static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
>> -{
>> -    u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN);
>> -
>> -    if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
>> -        !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
>> -        return -EIO;
>> -
>> -    return 0;
>> -}
>> -
>> -static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
>> -{
>> -    u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY);
>> -
>> -    if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
>> -        !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
>> -        return -EIO;
>> -
>> -    return 0;
>> -}
>> -
>>   static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev)
>>   {
>>       ivpu_boot_host_ss_rst_clr_assert(vdev);
>> @@ -396,37 +374,68 @@ static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
>>       return ivpu_boot_host_ss_axi_drive(vdev, true);
>>   }
>>   -static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
>> +static int ivpu_boot_host_ss_top_noc_qacceptn_check(struct ivpu_device *vdev, bool enable, u32 mask)
>> +{
>> +    u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN) & mask;
>> +
>> +    if (enable && val == mask)
>> +        return 0;
>> +
>> +    if (!enable && val == 0)
>> +        return 0;
>> +
>> +    ivpu_dbg(vdev, PM, "Failed qacceptn check 0x%x (mask 0x%x enable %d)\n", val, mask, enable);
>> +    return -EIO;
>> +}
>> +
>> +static int ivpu_boot_host_ss_top_noc_qdeny_check(struct ivpu_device *vdev, u32 mask)
>> +{
>> +    u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY) & mask;
>> +
>> +    if (val) {
>> +        ivpu_dbg(vdev, PM, "Failed qdeny check 0x%x (mask 0x%x)\n", val, mask);
>> +        return -EIO;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable, u32 mask)
>>   {
>> -    int ret;
>>       u32 val;
>>         val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
>> -    if (enable) {
>> -        val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
>> -        val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
>> -    } else {
>> -        val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
>> -        val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
>> -    }
>> -    REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val);
>> +    if (enable)
>> +        REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val | mask);
>> +    else
>> +        REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val & ~mask);
>>   -    ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
>> -    if (ret) {
>> -        ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
>> -        return ret;
>> -    }
>> +    if (!ivpu_boot_host_ss_top_noc_qacceptn_check(vdev, enable, mask))
>> +        return 0;
>>   -    ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
>> -    if (ret)
>> -        ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
>> +    if (!enable && ivpu_boot_host_ss_top_noc_qdeny_check(vdev, mask))
>> +        REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val | mask);
>>   -    return ret;
>> +    return -EIO;
>>   }
>>     static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
>>   {
>> -    return ivpu_boot_host_ss_top_noc_drive(vdev, true);
>> +    return ivpu_boot_host_ss_top_noc_drive(vdev, true,
>> +                           VPU_37XX_TOP_NOC_QREQN_CPU_CTRL_MASK |
>> +                           VPU_37XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK);
>> +}
>> +
>> +static int ivpu_boot_host_ss_top_noc_cpu_ctrl_disable(struct ivpu_device *vdev)
>> +{
>> +    return ivpu_boot_host_ss_top_noc_drive(vdev, false,
>> +                           VPU_37XX_TOP_NOC_QREQN_CPU_CTRL_MASK);
>> +}
>> +
>> +static int ivpu_boot_host_ss_top_noc_hostif_l2cache_disable(struct ivpu_device *vdev)
>> +{
>> +    return ivpu_boot_host_ss_top_noc_drive(vdev, false,
>> +                           VPU_37XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK);
>>   }
>>     static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
>> @@ -510,16 +519,6 @@ static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
>>       return ret;
>>   }
>>   -static int ivpu_boot_pwr_domain_disable(struct ivpu_device *vdev)
>> -{
>> -    ivpu_boot_dpu_active_drive(vdev, false);
>> -    ivpu_boot_pwr_island_isolation_drive(vdev, true);
>> -    ivpu_boot_pwr_island_trickle_drive(vdev, false);
>> -    ivpu_boot_pwr_island_drive(vdev, false);
>> -
>> -    return ivpu_boot_wait_for_pwr_island_status(vdev, 0x0);
>> -}
>> -
>>   static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
>>   {
>>       u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
>> @@ -618,19 +617,18 @@ static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev)
>>     static int ivpu_hw_37xx_reset(struct ivpu_device *vdev)
>>   {
>> -    int ret = 0;
>> +    int retries = 100;
>>   -    if (ivpu_boot_pwr_domain_disable(vdev)) {
>> -        ivpu_err(vdev, "Failed to disable power domain\n");
>> -        ret = -EIO;
>> -    }
>> +    while (ivpu_boot_host_ss_top_noc_cpu_ctrl_disable(vdev) && --retries > 0)
>> +        ivpu_warn(vdev, "Retrying to disable CPU control, retries left: %d\n", retries);
>>   -    if (ivpu_pll_disable(vdev)) {
>> -        ivpu_err(vdev, "Failed to disable PLL\n");
>> -        ret = -EIO;
>> -    }
>> +    while (ivpu_boot_host_ss_top_noc_hostif_l2cache_disable(vdev) && --retries > 0)
>> +        ivpu_warn(vdev, "Retrying to disable HostIf L2 Cache, retries left: %d\n", retries);
>>   -    return ret;
>> +    while (ivpu_pll_disable(vdev) && --retries > 0)
>> +        ivpu_warn(vdev, "Retrying to disable PLL, retries left: %d\n", retries);
>> +
>> +    return retries > 0 ? 0 : -EIO;
> 
> It seems weird that retries is never reset between operations.  Why is that?

This is intentional.
Retries are shared among all operations as we don't exacly know max number of retries for each of them.

Re: [PATCH 4/7] accel/ivpu: Gracefully shutdown NPU before reset

[Jacek Lawrynowicz]

On 05.02.2024 09:39, Jacek Lawrynowicz wrote:
> On 26.01.2024 19:23, Jeffrey Hugo wrote:
>> On 1/26/2024 5:28 AM, Jacek Lawrynowicz wrote:
>>> From: "Wachowski, Karol" <karol.wachowski@intel.com>
>>>
>>> Replace forceful disable of power domains with requests to disable
>>> TOP NOC CPU_CTRL and HOSTIF_L2CACHE through QREQN.
>>>
>>> In case of failure retry multiple times following HAS sequence of
>>> checking both QACCEPN and QDENYN registers.
>>>
>>> This fixes VPU hangs with PCODE released in January 2024 onwards.
>>>
>>> Fixes: 3f7c0634926d ("accel/ivpu/37xx: Fix hangs related to MMIO reset")
>>> Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
>>> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
>>> ---
>>>   drivers/accel/ivpu/ivpu_hw_37xx.c | 122 +++++++++++++++---------------
>>>   1 file changed, 60 insertions(+), 62 deletions(-)
>>>

...

>>>   static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
>>>   {
>>>       u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
>>> @@ -618,19 +617,18 @@ static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev)
>>>     static int ivpu_hw_37xx_reset(struct ivpu_device *vdev)
>>>   {
>>> -    int ret = 0;
>>> +    int retries = 100;
>>>   -    if (ivpu_boot_pwr_domain_disable(vdev)) {
>>> -        ivpu_err(vdev, "Failed to disable power domain\n");
>>> -        ret = -EIO;
>>> -    }
>>> +    while (ivpu_boot_host_ss_top_noc_cpu_ctrl_disable(vdev) && --retries > 0)
>>> +        ivpu_warn(vdev, "Retrying to disable CPU control, retries left: %d\n", retries);
>>>   -    if (ivpu_pll_disable(vdev)) {
>>> -        ivpu_err(vdev, "Failed to disable PLL\n");
>>> -        ret = -EIO;
>>> -    }
>>> +    while (ivpu_boot_host_ss_top_noc_hostif_l2cache_disable(vdev) && --retries > 0)
>>> +        ivpu_warn(vdev, "Retrying to disable HostIf L2 Cache, retries left: %d\n", retries);
>>>   -    return ret;
>>> +    while (ivpu_pll_disable(vdev) && --retries > 0)
>>> +        ivpu_warn(vdev, "Retrying to disable PLL, retries left: %d\n", retries);
>>> +
>>> +    return retries > 0 ? 0 : -EIO;
>>
>> It seems weird that retries is never reset between operations.  Why is that?
> 
> This is intentional.
> Retries are shared among all operations as we don't exacly know max number of retries for each of them.

We found a better solution to our stability issues. I will drop this patch and submit a new one.

Re: [PATCH 0/7] accel/ivpu fixes for 6.8-rc3

[Jacek Lawrynowicz]

Applied to drm-misc-fixes (except patch 4)

On 26.01.2024 13:27, Jacek Lawrynowicz wrote:
> A couple of small patches focused on improving driver stability.
> In addition d3hot_delay patch improves LNL inference latency.
> 
> Grzegorz Trzebiatowski (1):
>   accel/ivpu: Add job status for jobs aborted by the driver
> 
> Jacek Lawrynowicz (1):
>   accel/ivpu: Disable d3hot_delay on all NPU generations
> 
> Krystian Pradzynski (2):
>   accel/ivpu/40xx: Enable D0i3 message
>   accel/ivpu/40xx: Stop passing SKU boot parameters to FW
> 
> Wachowski, Karol (3):
>   accel/ivpu: Force snooping for MMU writes
>   accel/ivpu: Correct MMU queue size checking functions
>   accel/ivpu: Gracefully shutdown NPU before reset
> 
>  drivers/accel/ivpu/ivpu_drv.c     |   5 +-
>  drivers/accel/ivpu/ivpu_fw.c      |   1 -
>  drivers/accel/ivpu/ivpu_hw_37xx.c | 124 +++++++++++++++---------------
>  drivers/accel/ivpu/ivpu_hw_40xx.c |   7 +-
>  drivers/accel/ivpu/ivpu_job.c     |   4 +-
>  drivers/accel/ivpu/ivpu_mmu.c     |  36 +++++----
>  include/uapi/drm/ivpu_accel.h     |   1 +
>  7 files changed, 89 insertions(+), 89 deletions(-)
> 
> --
> 2.43.0