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From: Chris Wilson <chris@chris-wilson.co.uk>
To: Keith Packard <keithp@keithp.com>, Dave Airlie <airlied@redhat.com>
Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings
Date: Wed, 28 Sep 2011 10:09:13 +0100	[thread overview]
Message-ID: <aefc95$1m20sf@orsmga001.jf.intel.com> (raw)
In-Reply-To: <yunr531981s.fsf@aiko.keithp.com>

On Tue, 27 Sep 2011 11:03:43 -0700, Keith Packard <keithp@keithp.com> wrote:
Non-text part: multipart/signed
> On Tue, 27 Sep 2011 17:47:10 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > On Mon, 26 Sep 2011 23:11:43 -0700, Keith Packard <keithp@keithp.com> wrote:
> > > The PCH refclk settings are global, so we need to look at all of the
> > > encoders, not just the current encoder when deciding how to configure
> > > it. Also, handle systems with more than one panel (any combination of
> > > PCH/non-PCH eDP and LVDS).
> > 
> > As I read it, this sets the refclk not on the active configuration, but
> > on all the hardware detected for the system whether enabled or not.
> 
> Correct. We cannot randomly turn ref clocks on/off without also
> disconnecting them from the PLLs that they drive.
> 
> What we could do is figure out which of the two clocks need to be
> enabled and modify the mode set code to turn them on when needed before
> setting the mode, and then turn them off after, when they aren't
> needed. This would leave them off until needed, which might be nice?
> 
> This will make changing the driver to not disable the panel at startup
> time harder; we'll need to switch the panel to the non-SSC reference,
> turn the SSC reference off, reconfigure it and then switch the panel
> back to the SSC reference. That's a project for a future change though.

My understanding was that we could not enable SSC at all if we had a VGA,
DVI/HDMI or TV output; DP may or may not work with SSC.

The patch says that we will want to enable SSC if we have an SSC capbable
LVDS or eDP, which is certainly true. And that we can always do so if we
remember to set a magic bit in refclk to prevent non-SSC capable outputs
from being upset. I have not seen anything to support that last statement,
but, then again, I have not seen anything that actually explains what CK505
is!

Having said that, this is an obvious improvement over the current
situation in that we do choose correctly in more circumstances and we do
not reprogram the refclk whilst active.

As an incremental improvement [in my understanding ;-]:
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

  reply	other threads:[~2011-09-28  9:09 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <yunbou6lxb4.fsf@aiko.keithp.com>
2011-09-27  6:11 ` PCH reference clock cleanups Keith Packard
2011-09-27  6:11   ` [PATCH 1/9] drm/i915: broken copyright encoding in intel_bios.c Keith Packard
2011-09-27  6:11   ` [PATCH 2/9] drm/i915: Use DRM_DEBUG_KMS for all messages " Keith Packard
2011-09-27 16:39     ` Chris Wilson
2011-09-27  6:11   ` [PATCH 3/9] drv/i915: Pull display_clock_mode out of VBT table Keith Packard
2011-09-27 16:40     ` Chris Wilson
2011-09-27  6:11   ` [PATCH 4/9] drm/i915: Document a few more BDB_GENERAL_FEATURES bits from PCH BIOS Keith Packard
2011-09-27  6:11   ` [PATCH 5/9] drm/i915: Allow SSC parameter to override VBT value Keith Packard
2011-09-27 16:41     ` Chris Wilson
2011-09-27  6:11   ` [PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings Keith Packard
2011-09-27 16:47     ` Chris Wilson
2011-09-27 18:03       ` Keith Packard
2011-09-28  9:09         ` Chris Wilson [this message]
2011-09-28 16:36           ` Keith Packard
2011-09-27  6:11   ` [PATCH 7/9] drm/i915: Use CK505 as non-SSC source where available Keith Packard
2011-09-27 16:49     ` Chris Wilson
2011-09-27  6:11   ` [PATCH 8/9] drm/i915: All PCH refclks are 120MHz Keith Packard
2011-09-27 16:53     ` Chris Wilson
2011-09-27  6:11   ` [PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time Keith Packard
2011-09-27 16:56     ` Chris Wilson
2011-09-27 18:11       ` Keith Packard
2011-10-03 21:12         ` [Intel-gfx] " Jesse Barnes
2011-09-28 23:15     ` Keith Packard
2011-09-27  9:01   ` PCH reference clock cleanups Chris Wilson
2011-09-27 16:54     ` Keith Packard
2011-09-28 18:22   ` [Intel-gfx] " Paulo Zanoni
2011-09-28 20:02     ` Keith Packard
2011-10-03 21:14     ` Jesse Barnes
2011-10-03 23:18       ` [Intel-gfx] " Keith Packard
2011-10-03 23:21         ` Jesse Barnes
2011-10-03 23:39           ` Keith Packard

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