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[2003:e4:1f1b:da00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5aa5b00a5f4sm260919e87.0.2026.05.29.05.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 05:30:35 -0700 (PDT) Date: Fri, 29 May 2026 14:30:33 +0200 From: Thierry Reding To: Svyatoslav Ryhel Cc: Thierry Reding , Mikko Perttunen , David Airlie , Simona Vetter , Jonathan Hunter , Diogo Ivo , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 0/2 RESEND] gpu/drm: tegra: add DSI support for Tegra20/Tegra30 Message-ID: References: <20260511074538.24563-1-clamor95@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="ugsdrugixr4n33iu" Content-Disposition: inline In-Reply-To: <20260511074538.24563-1-clamor95@gmail.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --ugsdrugixr4n33iu Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v4 0/2 RESEND] gpu/drm: tegra: add DSI support for Tegra20/Tegra30 MIME-Version: 1.0 On Mon, May 11, 2026 at 10:45:35AM +0300, Svyatoslav Ryhel wrote: > Tegra20/Tegra30 DSI is quite similar to Tegra114+ apart MIPI calibration > logic and clocks. With a few minor tweaks, existing tegra DSI driver > should work on Tegra20/Tegra30 devices just fine. Tested on > Motorola Atrix 4G (T20) and ASUS VivoTab RT TF600T (T30). >=20 > This patchset depends on Tegra20/Tegra30 CSI bringup since both share > MIPI calibration logic. Ideally these patches should be picked after > CSI bringup but they will not break anything even if picked before > CSI patches. >=20 > --- > Changes in v2: > - removed all MIPI calibration, it is handled within CSI bringup > - added per-soc structures into of_match > - added fix for hang caused by register access with uninited hw >=20 > Changes in v3: > - switched from version DSI to boolean flags > - added comment regarding Tegra30 clock configuration > - commits were picked: > "clk: tegra20: reparent dsi clock to pll_d_out0" > "ARM: tegra: adjust DSI nodes for Tegra20/Tegra30" > - commit adapted to recent DSI changes: > "gpu/drm: tegra: dsi: move prepare function at the top of encoder > enable" > "gpu/drm: tegra: dsi: re-add clear enable register if > DSI was powered by bootloader" >=20 > Changes in v4: > - switched to device_get_match_data and added check > - added comment regarding Tegra124+ quirk > - adjusted commit titles and message formatting > --- >=20 > Svyatoslav Ryhel (2): > drm/tegra: dsi: add support for Tegra20/Tegra30 > drm/tegra: dsi: re-add clear enable register if DSI was powered by > bootloader >=20 > drivers/gpu/drm/tegra/drm.c | 2 + > drivers/gpu/drm/tegra/dsi.c | 126 +++++++++++++++++++++++++++--------- > drivers/gpu/drm/tegra/dsi.h | 10 +++ > 3 files changed, 107 insertions(+), 31 deletions(-) Applied, thanks. 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