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Fri, 17 Jul 2026 09:06:42 -0700 (PDT) Received: from owl5 ([2001:861:3201:3d10:d4b8:8874:bdef:21b2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4954ba2abd0sm37795105e9.15.2026.07.17.09.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2026 09:06:41 -0700 (PDT) Date: Fri, 17 Jul 2026 18:06:40 +0200 From: Gary Bisson To: Esben Haabendal Cc: AngeloGioacchino Del Regno , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Adam Thiede , Thorsten Leemhuis Subject: Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable Message-ID: References: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> <8733xko1ms.fsf@geanix.com> <0f719c00-3cf5-4403-afbf-713b07255981@collabora.com> <65558ccc-4f2c-492d-8c74-627d27dce864@collabora.com> <87h5m0mkca.fsf@geanix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87h5m0mkca.fsf@geanix.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Angelo & Esteban, On Wed, Jul 15, 2026 at 03:52:05PM +0200, Esben Haabendal wrote: > "AngeloGioacchino Del Regno" > writes: > > > On 7/15/26 15:36, Gary Bisson wrote: > >> Hi, > >> > >> On Wed, Jul 15, 2026 at 03:25:11PM +0200, AngeloGioacchino Del Regno wrote: > >>> On 7/15/26 14:53, Esben Haabendal wrote: > >>>> Gary Bisson writes: > >>>> > >>>>> Some bridges, such as the TI SN65DSI83, require the HS clock to be > >>>>> running in order to lock its PLL during its own pre-enable function. > >>>>> > >>>>> Without this change, the bridge gives the following error: > >>>>> sn65dsi83 14-002c: failed to lock PLL, ret=-110 > >>>>> sn65dsi83 14-002c: Unexpected link status 0x01 > >>>>> sn65dsi83 14-002c: reset the pipe > >>>>> > >>>>> Move the necessary functions from enable to pre-enable. > >>>>> > >>>>> Signed-off-by: Gary Bisson > >>>> > >>>> Hi > >>>> > >>>> I have run into the same problem, but in combination with another > >>>> pipeline. I am seeing same problem with an i.MX8 using the nwl-dsi > >>>> bridge and the dcss driver. > >>>> > >>>> I have submitted a fix that adresses the problem in the ti-sn65dsi83 > >>>> driver instead. With a bit of luck, it can replace the fix proposed in > >>>> this thread. > >>>> > >>>> See https://lore.kernel.org/all/20260711-ti-sn65dsi83-fixes-v1-2-d85eb5342b98@geanix.com/ > >> > >> Thanks, just tried it on 7.2-rc3 with my patch reverted and confirm that > >> it works too. My assumption was that the SN65DSI83 was locking the PLL > >> earlier for some specific reason and therefore was reluctant to change > >> it. > >> > >>>> /Esben > >>> > >>> That clarifies a lot of things. > >>> > >>> The patch on mtk_dsi shall be reverted then. > >> > >> Angelo, do you want me to offer the revert patch? Should I wait to see > >> how the other thread goes? > >> > > > > Gary, yes please, send a revert and make sure to explain the reason why > > we're reverting this in the commit description :-) > > Maybe test if my fix actually solves the problem with the mtk_dsi driver > also ;) As mentioned in the other thread, your patch works but it might break the init sequence recommended by the bridge datasheet. Moreover, the drm_bridge.c doc [1] does mention that the clock lane should be initialized during pre_enable. If we agree on this assumption I believe my patch should not be reverted. Maybe Adam's bridge driver must be patched instead, just like the nwl-dsi driver should be updated to follow the drm recommendation. Let me know your thoughts. Regards, Gary [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/drm_bridge.c#n169