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We do not need to enable up/down >> interrupts when SLPC is enabled. However, we still need the ARAT >> interrupt, which will be enabled separately later. >> > > Do we not need a check for rps_uses_slpc in intel_rps_enable? I guessing > there is a reason why we don't but can't seem to figure that out. Yeah, it's due to this check in there - if (rps->max_freq <= rps->min_freq) /* leave disabled, no room for dynamic reclocking */; With slpc, rps->max_freq and rps->min freq remain uninitialized, so the if condition just falls through and returns with this- if (!enabled) return; Thanks, Vinay. > > Matt > >> Signed-off-by: Vinay Belgaumkar >> Signed-off-by: Sundaresan Sujaritha >> --- >> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- >> drivers/gpu/drm/i915/gt/intel_rps.c | 20 ++++++++++++++++++++ >> 2 files changed, 21 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c >> index a64aa43f7cd9..04dd69bcf6cb 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt.c >> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c >> @@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) >> intel_gt_init_timelines(gt); >> intel_gt_pm_init_early(gt); >> >> - intel_rps_init_early(>->rps); >> intel_uc_init_early(>->uc); >> + intel_rps_init_early(>->rps); >> } >> >> int intel_gt_probe_lmem(struct intel_gt *gt) >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c >> index 0c8e7f2b06f0..e858eeb2c59d 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rps.c >> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c >> @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) >> return rps_to_gt(rps)->uncore; >> } >> >> +static bool rps_uses_slpc(struct intel_rps *rps) >> +{ >> + struct intel_gt *gt = rps_to_gt(rps); >> + >> + return intel_uc_uses_guc_slpc(>->uc); >> +} >> + >> static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask) >> { >> return mask & ~rps->pm_intrmsk_mbz; >> @@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps *rps) >> { >> struct intel_gt *gt = rps_to_gt(rps); >> >> + GEM_BUG_ON(rps_uses_slpc(rps)); >> + >> GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n", >> rps->pm_events, rps_pm_mask(rps, rps->last_freq)); >> >> @@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val) >> struct drm_i915_private *i915 = rps_to_i915(rps); >> u32 swreq; >> >> + GEM_BUG_ON(rps_uses_slpc(rps)); >> + >> if (GRAPHICS_VER(i915) >= 9) >> swreq = GEN9_FREQUENCY(val); >> else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) >> @@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps) >> { >> int adj; >> >> + if (!intel_rps_is_enabled(rps)) >> + return; >> + >> GEM_BUG_ON(atomic_read(&rps->num_waiters)); >> >> if (!intel_rps_clear_active(rps)) >> @@ -1829,6 +1843,9 @@ void intel_rps_init(struct intel_rps *rps) >> { >> struct drm_i915_private *i915 = rps_to_i915(rps); >> >> + if (rps_uses_slpc(rps)) >> + return; >> + >> if (IS_CHERRYVIEW(i915)) >> chv_rps_init(rps); >> else if (IS_VALLEYVIEW(i915)) >> @@ -1885,6 +1902,9 @@ void intel_rps_init(struct intel_rps *rps) >> >> void intel_rps_sanitize(struct intel_rps *rps) >> { >> + if (rps_uses_slpc(rps)) >> + return; >> + >> if (GRAPHICS_VER(rps_to_i915(rps)) >= 6) >> rps_disable_interrupts(rps); >> } >> -- >> 2.25.0 >>