From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CDF2C2B9F8 for ; Mon, 24 May 2021 18:12:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C176C600D1 for ; Mon, 24 May 2021 18:12:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C176C600D1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E660D6E214; Mon, 24 May 2021 18:12:30 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id DF4406E214; Mon, 24 May 2021 18:12:28 +0000 (UTC) IronPort-SDR: Uom0dkArOJsA1fqx3sQkH//72xcf6lkRZz8XDBITzsSFzlv9XEKxxsRVK5NRgcuddpmbv9t/P3 Wc8JPznMVVrA== X-IronPort-AV: E=McAfee;i="6200,9189,9993"; a="223155277" X-IronPort-AV: E=Sophos;i="5.82,325,1613462400"; d="scan'208";a="223155277" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2021 11:12:28 -0700 IronPort-SDR: MzMrCTn+8MtjrwfYKbbu/od2RURmBiVbMlUuQsB7YxDVefBLGLkeEc+1a1FJlOr5Q6TGYzyvXi 4vig1xd+o14A== X-IronPort-AV: E=Sophos;i="5.82,325,1613462400"; d="scan'208";a="475997705" Received: from clanggaa-mobl1.ger.corp.intel.com ([10.249.254.179]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2021 11:12:26 -0700 Message-ID: Subject: Re: [Intel-gfx] [PATCH v3 07/12] drm, drm/i915: Move the memcpy_from_wc functionality to core drm From: Thomas =?ISO-8859-1?Q?Hellstr=F6m?= To: Matthew Auld Date: Mon, 24 May 2021 20:12:23 +0200 In-Reply-To: References: <20210521153253.518037-1-thomas.hellstrom@linux.intel.com> <20210521153253.518037-8-thomas.hellstrom@linux.intel.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.38.4 (3.38.4-1.fc33) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter , Intel Graphics Development , Christian =?ISO-8859-1?Q?K=F6nig?= , ML dri-devel Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, 2021-05-24 at 17:45 +0100, Matthew Auld wrote: > On Fri, 21 May 2021 at 16:33, Thomas Hellström > wrote: > > > > Memcpy from wc will be used as well by TTM memcpy. > > Move it to core drm, and make the interface do the right thing > > even on !X86. > > > > Cc: Christian König > > Cc: Daniel Vetter > > Cc: Dave Airlie > > Signed-off-by: Thomas Hellström > > --- > > > > > + > > +#ifdef CONFIG_X86 > > +bool drm_memcpy_from_wc(void *dst, const void *src, unsigned long > > len); > > +bool drm_memcpy_from_wc_dbm(struct dma_buf_map *dst, > > +                           const struct dma_buf_map *src, > > +                           unsigned long len); > > +void drm_unaligned_memcpy_from_wc(void *dst, const void *src, > > unsigned long len); > > + > > +/* The movntdqa instructions used for memcpy-from-wc require 16- > > byte alignment, > > + * as well as SSE4.1 support. drm_memcpy_from_wc() will report if > > it cannot > > + * perform the operation. To check beforehand, pass in the > > parameters to > > + * drm_can_memcpy_from_wc() - since we only care about the low 4 > > bits, > > + * you only need to pass in the minor offsets, page-aligned > > pointers are > > + * always valid. > > + * > > + * For just checking for SSE4.1, in the foreknowledge that the > > future use > > + * will be correctly aligned, just use drm_has_memcpy_from_wc(). > > + */ > > +#define drm_can_memcpy_from_wc(dst, src, len) \ > > +       drm_memcpy_from_wc((void *)((unsigned long)(dst) | > > (unsigned long)(src) | (len)), NULL, 0) > > + > > +#define drm_has_memcpy_from_wc() \ > > +       drm_memcpy_from_wc(NULL, NULL, 0) > > + > > +void drm_memcpy_init_early(void); > > + > > +#else > > + > > +#define drm_memcpy_from_wc(_dst, _src, _len) (false) > > +#define drm_memcpy_from_wc_dbm(_dst, _src, _len) (false) > > +#define drm_can_memcpy_from_wc(_dst, _src, _len) (false) > > +#define drm_has_memcpy_from_wc() (false) > > Does the compiler not complain for these on !x86, if called without > checking the result of the statement? Maybe just make these function > stubs? > > Otherwise, > Reviewed-by: Matthew Auld Hmm, you're right. I'll fix. Thanks for reviewing! /Thomas