From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 108493] Unigine Heaven at 4K crashes amdgpu and causes a GPU hang Date: Mon, 29 Oct 2018 20:41:50 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0938630049==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A5086E0EA for ; Mon, 29 Oct 2018 20:41:50 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0938630049== Content-Type: multipart/alternative; boundary="15408457100.9ab05E7d.23792" Content-Transfer-Encoding: 7bit --15408457100.9ab05E7d.23792 Date: Mon, 29 Oct 2018 20:41:50 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated https://bugs.freedesktop.org/show_bug.cgi?id=3D108493 --- Comment #13 from Alex Deucher --- (In reply to Timur Krist=C3=B3f from comment #9) > OD_MCLK: > 0: 300MHz 750mV > 1: 1000MHz 800mV > 2: 1750MHz 900mV This is vddc. > [DEFAULT] ATOM_MCLK_ENTRY Array > ---- >=20 > Entry: 0 > Frequency: 300 MHz. > Voltage:. 1000 MV > Entry: 1 > Frequency: 1000 MHz. > Voltage:. 1000 MV > Entry: 2 > Frequency: 1750 MHz. > Voltage:. 1000 MV > ---- This is mvdd. these are not the same voltages. The pp_od_clk_voltage interface only allows you to adjust vddc. The vddc values match what is in= the vbios for your card. --=20 You are receiving this mail because: You are the assignee for the bug.= --15408457100.9ab05E7d.23792 Date: Mon, 29 Oct 2018 20:41:50 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated

Comme= nt # 13 on bug 10849= 3 from Alex Deucher 
(In reply to Timur Krist=C3=B3f from comment #9)

> OD_MCLK:
> 0:        300MHz        750mV
> 1:       1000MHz        800mV
> 2:       1750MHz        900mV

This is vddc.

> [DEFAULT] ATOM_MCLK_ENTRY Array
> ----
>=20
> Entry: 0
> 	Frequency: 300 MHz.
> 	Voltage:. 1000 MV
> Entry: 1
> 	Frequency: 1000 MHz.
> 	Voltage:. 1000 MV
> Entry: 2
> 	Frequency: 1750 MHz.
> 	Voltage:. 1000 MV
> ----

This is mvdd.  these are not the same voltages.  The pp_od_clk_voltage
interface only allows you to adjust vddc.  The vddc values match what is in=
 the
vbios for your card.

You are receiving this mail because:
  • You are the assignee for the bug.
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