| What | Removed | Added |
|---|---|---|
| Status | RESOLVED | CLOSED |
(In reply to Chris Wilson from comment #10) > commit 7fa28e146994da1e8a4124623d7da97b798ea520 = (HEAD -> > drm-intel-next-queued, drm-intel/for-linux-next, > drm-intel/drm-intel-next-queued) > Author: Chris Wilson <chris@chris-wilson.co.uk> > Date: Mon Nov 19 15:41:53 2018 +0000 >=20 > drm/i915: Write GPU relocs harder with gen3 >=20=20=20=20=20 > Under moderate amounts of GPU stress, we can observe on Bearlake a= nd > Pineview (later gen3 models) that we execute the following batch b= uffer > before the write into the batch is coherent. Adding extra (tested = with > upto 32x) MI_FLUSH to either the invalidation, flush or both phase= s does > not solve the incoherency issue with the relocations, but emitting= the > MI_STORE_DWORD_IMM twice does. So be it. >=20=20=20=20=20 > Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processi= ng") > Testcase: igt/gem_tiled_fence_blits # blb/pnv > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Link: > https://patchwork.freedesktop.org/patch/msgid/20181119154153.153= 27-1- > chris@chris-wilson= .co.uk Oddly-enough, this was not sufficient to fix the issue, but it stopped fail= ing after drmtip_176 (https://intel-gfx-ci.01.org/= tree/drm-tip/drmtip_176/fi-gdg-551/igt@gem_tiled_fence_blits@normal= .html), so closing!