From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 108591] [CI][DRMTIP] igt@gem_tiled_fence_blits@normal - fail - Failed assertion: linear[i] == start_val Date: Tue, 20 Nov 2018 09:53:34 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1311690573==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [IPv6:2610:10:20:722:a800:ff:fe98:4b55]) by gabe.freedesktop.org (Postfix) with ESMTP id 786416E369 for ; Tue, 20 Nov 2018 09:53:34 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============1311690573== Content-Type: multipart/alternative; boundary="15427076142.b4d9CC4e.31269" Content-Transfer-Encoding: 7bit --15427076142.b4d9CC4e.31269 Date: Tue, 20 Nov 2018 09:53:34 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated https://bugs.freedesktop.org/show_bug.cgi?id=3D108591 Chris Wilson changed: What |Removed |Added ---------------------------------------------------------------------------- Status|REOPENED |RESOLVED Resolution|--- |FIXED --- Comment #10 from Chris Wilson --- commit 7fa28e146994da1e8a4124623d7da97b798ea520 (HEAD -> drm-intel-next-que= ued, drm-intel/for-linux-next, drm-intel/drm-intel-next-queued) Author: Chris Wilson Date: Mon Nov 19 15:41:53 2018 +0000 drm/i915: Write GPU relocs harder with gen3 Under moderate amounts of GPU stress, we can observe on Bearlake and Pineview (later gen3 models) that we execute the following batch buffer before the write into the batch is coherent. Adding extra (tested with upto 32x) MI_FLUSH to either the invalidation, flush or both phases does not solve the incoherency issue with the relocations, but emitting the MI_STORE_DWORD_IMM twice does. So be it. Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing") Testcase: igt/gem_tiled_fence_blits # blb/pnv Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20181119154153.15327-1-chris@= chris-wilson.co.uk --=20 You are receiving this mail because: You are the assignee for the bug.= --15427076142.b4d9CC4e.31269 Date: Tue, 20 Nov 2018 09:53:34 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated Chris Wilson changed bug 10859= 1
What Removed Added
Status REOPENED RESOLVED
Resolution --- FIXED

Comme= nt # 10 on bug 10859= 1 from Chris Wilson 
commit 7fa28e146994da1e8a4124623d7da97b798ea520 (HEAD -> dr=
m-intel-next-queued,
drm-intel/for-linux-next, drm-intel/drm-intel-next-queued)
Author: Chris Wilson <ch=
ris@chris-wilson.co.uk>
Date:   Mon Nov 19 15:41:53 2018 +0000

    drm/i915: Write GPU relocs harder with gen3

    Under moderate amounts of GPU stress, we can observe on Bearlake and
    Pineview (later gen3 models) that we execute the following batch buffer
    before the write into the batch is coherent. Adding extra (tested with
    upto 32x) MI_FLUSH to either the invalidation, flush or both phases does
    not solve the incoherency issue with the relocations, but emitting the
    MI_STORE_DWORD_IMM twice does. So be it.

    Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing&qu=
ot;)
    Testcase: igt/gem_tiled_fence_blits # blb/pnv
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
    Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
    Link:
https://patchwork.freedesktop.org/patch/=
msgid/20181119154153.15327-1-chris@chris-wilson.co.uk

You are receiving this mail because:
  • You are the assignee for the bug.
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