From mboxrd@z Thu Jan 1 00:00:00 1970
From: bugzilla-daemon@freedesktop.org
Subject: [Bug 109303] [CI][SHARDS]
igt@i915_query@query-topology-known-pci-ids - skip - Test requirement:
IS_HASWELL(devid) || IS_BROADWELL(devid) || IS_SKYLAKE(devid) ||
IS_KABYLAKE(devid) || IS_COFFEELAKE(devid), SKIP
Date: Fri, 11 Jan 2019 10:43:44 +0000
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Date: Fri, 11 Jan 2019 10:43:44 +0000
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Auto-Submitted: auto-generated
https://bugs.freedesktop.org/show_bug.cgi?id=3D109303
Lionel Landwerlin changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |NEEDINFO
--- Comment #2 from Lionel Landwerlin =
---
(In reply to Martin Peres from comment #0)
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5388/shard-iclb2/
> igt@i915_query@query-topology-known-pci-ids.html
>=20
> Test requirement: IS_HASWELL(devid) || IS_BROADWELL(devid) ||
> IS_SKYLAKE(devid) || IS_KABYLAKE(devid) || IS_COFFEELAKE(devid)
> Subtest query-topology-known-pci-ids: SKIP (0.000s)
>=20
> I doubt that this would only be supported on these platforms and not on C=
NL
> and ICL.
It does only support haswell/gen8/gen9 because that's the only place where
based off the GT we can deduct the number of slices/subslices and do some
actual checks on the values returned by i915.
On gen10+ fusing is a lot more fuzzy.
One way to extend coverage would be to beef up lib/intel_device_info.c to
contain information about the topology of the device.
Thoughts welcome.
--=20
You are receiving this mail because:
You are the assignee for the bug.=
--15472034240.E773f.5681
Date: Fri, 11 Jan 2019 10:43:44 +0000
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Auto-Submitted: auto-generated
Lionel Landwerlin
changed
bug 10930=
3
| What |
Removed |
Added |
| Status |
NEW
|
NEEDINFO
|
Commen=
t # 2
on bug 10930=
3
from Lionel Landwe=
rlin
(In reply to Martin Peres from comment #0)
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_D=
RM_5388/shard-iclb2/
> igt@i915_query@query-topology-known-pci-ids.html
>=20
> Test requirement: IS_HASWELL(devid) || IS_BROADWELL(devid) ||
> IS_SKYLAKE(devid) || IS_KABYLAKE(devid) || IS_COFFEELAKE(devid)
> Subtest query-topology-known-pci-ids: SKIP (0.000s)
>=20
> I doubt that this would only be supported on these platforms and not o=
n CNL
> and ICL.
It does only support haswell/gen8/gen9 because that's the only place where
based off the GT we can deduct the number of slices/subslices and do some
actual checks on the values returned by i915.
On gen10+ fusing is a lot more fuzzy.
One way to extend coverage would be to beef up lib/intel_device_info.c to
contain information about the topology of the device.
Thoughts welcome.
You are receiving this mail because:
- You are the assignee for the bug.
=
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