From: bugzilla-daemon@bugzilla.kernel.org
To: dri-devel@lists.freedesktop.org
Subject: [Bug 172421] radeon: allow to set the TMDS frequency by a special kernel parameter
Date: Tue, 27 Nov 2018 03:33:29 +0000 [thread overview]
Message-ID: <bug-172421-2300-ZDa6Ycm1hR@https.bugzilla.kernel.org/> (raw)
In-Reply-To: <bug-172421-2300@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=172421
John (sirfixabyte@gmail.com) changed:
What |Removed |Added
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CC| |sirfixabyte@gmail.com
--- Comment #19 from John (sirfixabyte@gmail.com) ---
I read all the previous comments - for and against the adoption of the patch.
Question: Why is it easy to find a pixel clock patch for WINDOWS
(www.monitortests.com AMD/ATI Pixel Clock Patcher by someone named 'ToastyX')
-available and supported since 2012 - and successfully running 4K screens
(since January 2016) on the same Radeon cards being discussed here ? Many
people on that webpage discussing it. Seems to work. I personally tested on a
few older Radeon cards and it works at 3840x2160 for me. I have NOT yet run it
for hours (I rarely run Windows, and then only to test of fix PC's for others).
I have not connected temperature sensors to heat sinks yet.
If the pixel clock generator circuitry is on the same die as everything else,
then it shares a heat sink. The whole thing designed such that with
recommended airflow across that heat sink, the GPU remains functional. BUT,
that can mean running 3 separate displays - utilizing the full capacity of the
GPU.
IF this patch from Elmar Stellnberger were to be used to run a SINGLE 4K LCD at
3840 x 2160 at 30% overclock on the pixel clock generator, maybe the overall
GPU would be generating much less than maximum heat, and the heatsink/fan could
easily keep it cool.
Does anyone have a maximum pixel clock specification for the various pixel
clock generator designs on the various ATI/AMD dies ?
Did ATI set limits due to HDMI cables and overall ability of heatsink to
dissipate the heat when running the GPU at max speed / load on 3 screens ?
Is there a listed maximum voltage that the PLL can run at - long term - without
damage ? for most integrated circuits data sheets I have ever read, there is a
relationship between max speed and temperature of the die.
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next prev parent reply other threads:[~2018-11-27 3:33 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-21 18:15 [Bug 172421] New: radeon: allow to set the TMDS frequency by a special kernel parameter bugzilla-daemon
2016-09-21 18:16 ` [Bug 172421] " bugzilla-daemon
2016-09-21 18:17 ` bugzilla-daemon
2016-09-21 18:30 ` bugzilla-daemon
2016-09-21 18:37 ` bugzilla-daemon
2016-09-21 18:38 ` bugzilla-daemon
2016-09-21 18:49 ` bugzilla-daemon
2016-09-21 19:59 ` bugzilla-daemon
2016-09-21 20:16 ` bugzilla-daemon
2016-09-21 20:20 ` bugzilla-daemon
2016-09-22 7:07 ` bugzilla-daemon
2016-09-22 7:24 ` bugzilla-daemon
2016-09-22 13:51 ` bugzilla-daemon
2016-09-23 2:53 ` bugzilla-daemon
2016-09-23 7:36 ` bugzilla-daemon
2016-09-23 16:22 ` bugzilla-daemon
2016-09-23 17:27 ` bugzilla-daemon
2016-09-24 18:08 ` bugzilla-daemon
2017-12-16 18:52 ` bugzilla-daemon
2018-11-27 3:33 ` bugzilla-daemon [this message]
2018-11-27 12:28 ` bugzilla-daemon
2019-02-23 12:44 ` bugzilla-daemon
2022-06-19 15:33 ` bugzilla-daemon
2022-06-19 15:43 ` bugzilla-daemon
2023-01-03 12:16 ` bugzilla-daemon
2023-04-04 8:21 ` bugzilla-daemon
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