Comment # 12 on bug 56139 from Alex Deucher

(In reply to comment #11)
> Found what is wrong with the help of a few printk and by comparing to the
> code being replaced. All the logic is good (going through crtc, disabling
> them, waiting for vblank) BUT setting "tmp |=
> EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;" is wrong.
> 
> If I do as in the previous code by setting tmp = 0 and then continuing with:
> radeon_wait_for_vblank(rdev, i);
> WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
> everything works fine as before.
> 
> What is expected from "tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;"?
> From what I read with printk, it is far from a 0 or a 1. Is this normal?

That's the most important bit in the entire sequence.  It's a bit field in a
register (bit 24 to be exact).  That bit is the bit that actually disables the
requests from the display controller in the memory controller.  The whole point
of this code is to disable all clients of the memory controller (mc_stop()) so
that we can change the location of vram within the GPU's address space.  Once
we've moved vram, we can re-enable the clients (mc_resume()) so that they point
to the new vram location.