Commen=
t # 30
on bug 56139<=
/a>
from Alexandre Demers
(In reply to comment #=
29)
> (In reply to comment #28)
> > Alex, a simple question: you said bit 0 in EVERGREEN_CRTC_CONTROL=
stops the
> > CRTC sync. With the culprit commit, when is it set? I mean, I had=
a quick
> > look in the driver's code and I couldn't find it. When going in s=
uspend
> > state, shouldn't it be set to 0? Then, on resume, shouldn't it be=
set to 1?
> > I may just have missed it, but could this be something missing? S=
ame
> > questions goes for GPU soft reset.
>=20
> It's set by the vbios at boot before the OS loads. Once the driver lo=
ads,
> it's then handled by the modesetting code. crtcs are enabled or disab=
led
> based on what's connected and what displays the user has chosen to ena=
ble.
>=20
> These functions have nothing to do with system suspend/hibernate and r=
esume
> directly. evergreen_mc_stop() and evergreen_mc_resume() are for disab=
ling
> MC clients when we make changes to the GPU memory controller. System
> suspend/hibernate are handled by radeon_suspend_kms() and
> radeon_resume_kms(). radeon_suspend_kms() explicitly disables all of =
the
> display hardware:
>=20
> list_for_each_entry(connector, &dev->mode_config.connector_list=
, head) {
> drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
> }
>=20
> And then the displays are enabled again in radeon_resume_kms():
>=20
> /* blat the mode back in */
> drm_helper_resume_force_mode(dev);
> /* turn on display hw */
> list_for_each_entry(connector, &dev->mode_config.connector_list=
, head) {
> drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
> }
>=20
> >=20
> > Before the culprit commit, we were setting bit 0 to 0 on stop and=
setting it
> > back to 1 on resume, which was working great. Why aren't we doing=
it anymore
> > when suspending and resuming?
>=20
> The previous code[1] didn't do that. It set bit 0 to 0 in
> evergreen_mc_stop() and then left it disabled in evergreen_mc_resume()=
. The
> crtc was not subsequently re-enabled until the displays were set up la=
ter by
> the modesetting code. Prior to that patch[1], we just saved and resto=
red
> the value of the register which is basically what you are proposing, b=
ut
> that didn't work otherwise we wouldn't have needed the subsequent patc=
hes.
>=20
> We'd like to avoid disabling the crtc during driver load or GPU reset =
to
> avoid the visible flicker it causes.
>=20
> [1]:
> http://git.kernel.org/?p=3Dlinux/kernel/git/torvalds/li=
nux.git;a=3Dcommitdiff;
> h=3D81ee8fb6b52ec69eeed37fe7943446af1dccecc5
Your explanations are appreciated, but that kills another idea. By the way,
pictures and videos are coming, my camera had no power yesterday and I had =
to
charge it during last night.