Comment # 26
on bug 69723
from Alexandre Demers
Alex, in drivers/gpu/drm/radeon/ni_dpm.c, when we are limiting the sclk and
mclk to the max speed according to vddc and vddci, aren't we screwing possibly
something with mclk? I mean, could we be setting a mclk value that is wrong? We
have two conditions where we can max mclk value, but we are not looking at the
lowest one. I think it should be something like this instead to be sure we are
using the most restrictive value:
/* Select the lowest mclk value according to the most restrictive between
vddc and vddci*/
if (max_mclk_vddc || max_mclk_vddci) {
max_mclk_vddcx = (max_mclk_vddc > max_mclk_vddci) ? max_mclk_vddci :
max_mclk_vddc;
}
for (i = 0; i < ps->performance_level_count; i++) {
if (max_sclk_vddc) {
if (ps->performance_levels[i].sclk > max_sclk_vddc)
ps->performance_levels[i].sclk = max_sclk_vddc;
}
if (max_mclk_vddcx) {
if (ps->performance_levels[i].mclk > max_mclk_vddcx)
ps->performance_levels[i].mclk = max_mclk_vddcx;
}
}
I'm also quoting you: "Not exactly. Mclk is tied to vddci (memory interface
voltage), but both mclk and sclk (and the core display clock) are tied to vddc
(core voltage)." Which means, mclk shouldn't run at its max speed if vddc is
not at its max value, isn't it? Otherwise, we may encounter stability problem.