From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 69723] GPU lockups with kernel 3.11.0 / 3.12-rc1 when dpm=1 on r600g (Cayman) Date: Wed, 27 Nov 2013 06:04:58 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0373861491==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 47ED9FAE4D for ; Tue, 26 Nov 2013 22:04:58 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0373861491== Content-Type: multipart/alternative; boundary="1385532298.8ED0dE052.6899"; charset="us-ascii" --1385532298.8ED0dE052.6899 Date: Wed, 27 Nov 2013 06:04:58 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" https://bugs.freedesktop.org/show_bug.cgi?id=69723 --- Comment #45 from Alex Deucher --- The windows driver should operate pretty much the same as the linux driver as far as I know. I'm not really familiar with how gpu-z reads back the clocks and voltages and that may have something to do with the differences. Not all of the aspects of the level transition happen at the same time. You could try setting the vddc to 1060 and changing the mclk of level 1 (mid level) to 650Mhz. Perhaps the jump from 150 to 1300 is too big and the pll is not able to lock properly. -- You are receiving this mail because: You are the assignee for the bug. --1385532298.8ED0dE052.6899 Date: Wed, 27 Nov 2013 06:04:58 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8"

Comment # 45 on bug 69723 from 
The windows driver should operate pretty much the same as the linux driver as
far as I know.  I'm not really familiar with how gpu-z reads back the clocks
and voltages and that may have something to do with the differences.  Not all
of the aspects of the level transition happen at the same time.

You could try setting the vddc to 1060 and changing the mclk of level 1 (mid
level) to 650Mhz.  Perhaps the jump from 150 to 1300 is too big and the pll is
not able to lock properly.

You are receiving this mail because:
  • You are the assignee for the bug.
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