From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 69723] Computer freezes with kernel 3.11.0 / 3.12-rc1 (with bug 68235's patches applied) when dpm=1 on r600g (Cayman) Date: Tue, 01 Oct 2013 13:19:25 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0712041917==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 9CC71E5D74 for ; Tue, 1 Oct 2013 06:19:25 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0712041917== Content-Type: multipart/alternative; boundary="1380633565.cDC1Fa0.9857"; charset="us-ascii" --1380633565.cDC1Fa0.9857 Date: Tue, 1 Oct 2013 13:19:25 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" https://bugs.freedesktop.org/show_bug.cgi?id=69723 --- Comment #11 from Alex Deucher --- (In reply to comment #10) > Just to be sure: vddc is associated only to sclk and vddci to mclk, right? > Not exactly. Mclk is tied to vddci (memory interface voltage), but both mclk and sclk (and the core display clock) are tied to vddc (core voltage). > Also, how are a new freq and a new voltage applied to the card? Are they > applied simultanously or sequentially? In the second case, we must be sure > to raise voltage before frequency when pushing the performances up, while we > should low the frequency before lowering the voltage when we are slowing > down. The actual adjustments are done by a microcontroller on the GPU. You pass a set of structures defining the performance levels within the power state to the microcontroller and the microcontroller handles the switching. It takes into account all of the ordering and chip state dependencies. -- You are receiving this mail because: You are the assignee for the bug. --1380633565.cDC1Fa0.9857 Date: Tue, 1 Oct 2013 13:19:25 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8"

Comment # 11 on bug 69723 from 
(In reply to comment #10)
> Just to be sure: vddc is associated only to sclk and vddci to mclk, right?
> 

Not exactly.  Mclk is tied to vddci (memory interface voltage), but both mclk
and sclk (and the core display clock) are tied to vddc (core voltage).

> Also, how are a new freq and a new voltage applied to the card? Are they
> applied simultanously or sequentially? In the second case, we must be sure
> to raise voltage before frequency when pushing the performances up, while we
> should low the frequency before lowering the voltage when we are slowing
> down.

The actual adjustments are done by a microcontroller on the GPU.  You pass a
set of structures defining the performance levels within the power state to the
microcontroller and the microcontroller handles the switching.  It takes into
account all of the ordering and chip state dependencies.

You are receiving this mail because:
  • You are the assignee for the bug.
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