From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks! Date: Mon, 16 Feb 2015 21:15:37 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1792740643==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id E74AA6E10B for ; Mon, 16 Feb 2015 13:15:37 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============1792740643== Content-Type: multipart/alternative; boundary="1424121337.5ea872.27154"; charset="UTF-8" --1424121337.5ea872.27154 Date: Mon, 16 Feb 2015 21:15:37 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable https://bugs.freedesktop.org/show_bug.cgi?id=3D73378 --- Comment #37 from Chernovsky Oleg --- Created attachment 113544 --> https://bugs.freedesktop.org/attachment.cgi?id=3D113544&action=3Dedit fglrx mmiotrace dump (In reply to Christian K=C3=B6nig from comment #36) > Well it might already help if you provide the values for the UPLL registe= rs > together under fglrx, so that we can compare them to the values Radeon us= es. >=20 > Regards, > Christian. Just thought about that. Here it is, quite near the place where first related register R/W occured. --=20 You are receiving this mail because: You are the assignee for the bug. --1424121337.5ea872.27154 Date: Mon, 16 Feb 2015 21:15:37 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Commen= t # 37 on bug 73378<= /a> from = Chernovsky Oleg 
Created attachment 113544 [details]
fglrx mmiotrace dump

(In reply to Christian K=C3=B6nig from comment #36)
> Well it might already help if you provide the va=
lues for the UPLL registers
> together under fglrx, so that we can compare them to the values Radeon=
 uses.
>=20
> Regards,
> Christian.

Just thought about that.
Here it is, quite near the place where first related register R/W occured.<=
/pre>

You are receiving this mail because: =20=20=20=20=20=20
  • You are the assignee for the bug.
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