From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks! Date: Thu, 29 Jan 2015 10:44:43 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0918225753==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A4D96E739 for ; Thu, 29 Jan 2015 02:44:43 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0918225753== Content-Type: multipart/alternative; boundary="1422528283.Ec08b8653.29946"; charset="UTF-8" --1422528283.Ec08b8653.29946 Date: Thu, 29 Jan 2015 10:44:43 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable https://bugs.freedesktop.org/show_bug.cgi?id=3D73378 --- Comment #20 from Christian K=C3=B6nig --- (In reply to Chernovsky Oleg from comment #15) > I can help with code here. >=20 > What should be implemented, roughly? Sounds good. I assume you got a card with that problem. First of all try if UVD works otherwise. E.g. we raise the clocks for the b= oot up test (and lower them again after that), but that's actually not necessary most of the time. So get into radeon_uvd_send_upll_ctlreq, just comment out the error return value and pretend everything worked fine. Then check if the following IB test works or not. If that doesn't work the input clocks to the PLL doesn't seem to work and we have a clock routing problem or something like that. If that works the PLL = just doesn't likes our parameters and we need to figure out why. Feel free to contact me by mail if you have more questions. Thanks, Christian. --=20 You are receiving this mail because: You are the assignee for the bug. --1422528283.Ec08b8653.29946 Date: Thu, 29 Jan 2015 10:44:43 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Commen= t # 20 on bug 73378<= /a> from Christian K=C3=B6nig 
(In reply to Chernovsky Oleg from comment #15)
> I can help with code here.
>=20
> What should be implemented, roughly?

Sounds good. I assume you got a card with that problem.

First of all try if UVD works otherwise. E.g. we raise the clocks for the b=
oot
up test (and lower them again after that), but that's actually not necessary
most of the time.

So get into radeon_uvd_send_upll_ctlreq, just comment out the error return
value and pretend everything worked fine.

Then check if the following IB test works or not.

If that doesn't work the input clocks to the PLL doesn't seem to work and we
have a clock routing problem or something like that. If that works the PLL =
just
doesn't likes our parameters and we need to figure out why.

Feel free to contact me by mail if you have more questions.

Thanks,
Christian.

You are receiving this mail because: =20=20=20=20=20=20
  • You are the assignee for the bug.
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