From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks! Date: Sat, 31 Jan 2015 10:18:06 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1407394354==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id F0CEC6E212 for ; Sat, 31 Jan 2015 02:18:06 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============1407394354== Content-Type: multipart/alternative; boundary="1422699486.83f38E83.26918"; charset="UTF-8" --1422699486.83f38E83.26918 Date: Sat, 31 Jan 2015 10:18:06 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable https://bugs.freedesktop.org/show_bug.cgi?id=3D73378 --- Comment #24 from Christian K=C3=B6nig --- (In reply to Chernovsky Oleg from comment #23) > Wow! Pls forget my last comment completely. >=20 > Just tried to watch H264 video and it was slow as hell :( Which is the espected result if you don't setup the clocks :) In this case the UVD block runs with the default 100Mhz instead of the desi= red 400,500,900 or whatever the power tables say we should programm it to. At l= east we now knew that the input frequency works well. Now take a look at si_set_uvd_clocks in si.c. Especially try to figure out = if the first or the second call to radeon_uvd_send_upll_ctlreq fails. Additional to that please install radeontool and get me the content of the CG_UPLL_* registers. E.g. I need the output of: radeontool regmatch 0x634 radeontool regmatch 0x638 radeontool regmatch 0x63c radeontool regmatch 0x644 radeontool regmatch 0x648 radeontool regmatch 0x650 Thanks, Christian. --=20 You are receiving this mail because: You are the assignee for the bug. --1422699486.83f38E83.26918 Date: Sat, 31 Jan 2015 10:18:06 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Commen= t # 24 on bug 73378<= /a> from Christian K=C3=B6nig 
(In reply to Chernovsky Oleg from comment #23)
> Wow! Pls forget my last comment completely.
>=20
> Just tried to watch H264 video and it was slow as hell :(

Which is the espected result if you don't setup the clocks :)

In this case the UVD block runs with the default 100Mhz instead of the desi=
red
400,500,900 or whatever the power tables say we should programm it to. At l=
east
we now knew that the input frequency works well.

Now take a look at si_set_uvd_clocks in si.c. Especially try to figure out =
if
the first or the second call to radeon_uvd_send_upll_ctlreq fails.

Additional to that please install radeontool and get me the content of the
CG_UPLL_* registers. E.g. I need the output of:

radeontool regmatch 0x634
radeontool regmatch 0x638
radeontool regmatch 0x63c
radeontool regmatch 0x644
radeontool regmatch 0x648
radeontool regmatch 0x650

Thanks,
Christian.

You are receiving this mail because: =20=20=20=20=20=20
  • You are the assignee for the bug.
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