From mboxrd@z Thu Jan 1 00:00:00 1970
From: bugzilla-daemon@freedesktop.org
Subject: [Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout
setting UVD clocks!
Date: Fri, 06 Feb 2015 09:19:23 +0000
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https://bugs.freedesktop.org/show_bug.cgi?id=3D73378
--- Comment #30 from Christian K=C3=B6nig ---
(In reply to Chernovsky Oleg from comment #29)
> No luck. Tried various hacks and commenting return values.
>=20
> Will try mmiotracing these registers from fglrx on weekend
Be careful that to write no irrational values into the PLL registers, e.g.
don't use partly radeon partly fglrx settings.
I once over clocked UVD to 4GHz instead of 400MHz by accident and the card =
is
still working, but at least in theory you can damage the hardware with that.
--=20
You are receiving this mail because:
You are the assignee for the bug.
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Date: Fri, 6 Feb 2015 09:19:22 +0000
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Commen=
t # 30
on bug 73378<=
/a>
from Christian K=C3=B6nig
(In reply to Chernovsky Oleg from comment #29)
> No luck. Tried various hacks and commenting retu=
rn values.
>=20
> Will try mmiotracing these registers from fglrx on weekend
Be careful that to write no irrational values into the PLL registers, e.g.
don't use partly radeon partly fglrx settings.
I once over clocked UVD to 4GHz instead of 400MHz by accident and the card =
is
still working, but at least in theory you can damage the hardware with that=
.
You are receiving this mail because:
=20=20=20=20=20=20
- You are the assignee for the bug.
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