[Bug 75241] radeon_compute_pll_avivo broken in 3.15-rc3

[bugzilla-daemon@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=75241

--- Comment #6 from Christian König <deathsimple@vodafone.de> ---
(In reply to Clemens Ladisch from comment #5)
> It's an Eizo S2100, but this should not matter because the clocks seen by the
> monitor are always about the same (162MHz/75kHz/60Hz).  If some were out of
> range, the monitor would show an error message, but with the PLL problem, the
> monitor does not appear to detect even an out-of-range signal.   I'd guess
> the
> PLL itself cannot handle the parameters.

The PLL should be able to handle this quite fine. It's just that when you
increase the reference and post divider you can better match the wanted
frequency for the cost of increased jitter and general signal stability.

I have one monitor here that practically works with everything I give to it,
another one can't handle it when the frequency doesn't precisely match and a
third one doesn't like it when we have a high jitter in the signal.

The trick is to find the right sweet spot where you can make everbody happy.

> The largest working ref_div_max limit is 131.

Thanks allot, going to use 128 then (just because it's a nice round number)
until somebody else starts to complain that his monitor doesn't likes the
signal.

Christian.

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