[Bug 75241] New: radeon_compute_pll_avivo broken in 3.15-rc3 - bugzilla-daemon

From: bugzilla-daemon@bugzilla.kernel.org
To: dri-devel@lists.freedesktop.org
Subject: [Bug 75241] New: radeon_compute_pll_avivo broken in 3.15-rc3
Date: Thu, 01 May 2014 13:51:26 +0000	[thread overview]
Message-ID: <bug-75241-2300@https.bugzilla.kernel.org/> (raw)

https://bugzilla.kernel.org/show_bug.cgi?id=75241

            Bug ID: 75241
           Summary: radeon_compute_pll_avivo broken in 3.15-rc3
           Product: Drivers
           Version: 2.5
    Kernel Version: 3.15-rc3
          Hardware: All
                OS: Linux
              Tree: Mainline
            Status: NEW
          Severity: high
          Priority: P1
         Component: Video(DRI - non Intel)
          Assignee: drivers_video-dri@kernel-bugs.osdl.org
          Reporter: clemens@ladisch.de
        Regression: Yes

After upgrading from rc2 to rc3, my RS880 no longer outputs a signal
that my monitor is able to show.

Bisected to this:

commit c2fb3094669a3205f16a32f4119d0afe40b1a1fd
Author: Christian König <christian.koenig@amd.com>
Date:   Sun Apr 20 13:24:32 2014 +0200

    drm/radeon: improve PLL limit handling in post div calculation

    This improves the PLL parameters when we work at
    the limits of the allowed ranges.

Debug output with black screen:

kernel: [drm:drm_crtc_helper_set_config] attempting to set mode from userspace
kernel: [drm:drm_mode_debug_printmodeline] Modeline 29:"1600x1200" 60 162000
1600 1664 1856 2160 1200 1201 1204 1250 0x48 0x5
kernel: [drm:radeon_encoder_set_active_device] setting active device to
00000200 from 00000200 00000200 for encoder 2
kernel: [drm:drm_crtc_helper_set_mode] [CRTC:14]
kernel: [drm:radeon_atom_encoder_dpms] encoder dpms 21 to mode 3, devices
00000001, active_devices 00000000
kernel: [drm:radeon_compute_pll_avivo] 162000 - 161990, pll dividers - fb:
2036.3 ref: 30, post 6

With this commit reverted (and working screen):

kernel: [drm:radeon_compute_pll_avivo] 162000 - 16106, pll dividers - fb:
1023.5 ref: 13, post 7

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