From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 76564] [AMD Fusion E-350] HDMI refresh rates doesn't match expectations Date: Wed, 26 Mar 2014 20:50:38 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1231901836==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 475D16E794 for ; Wed, 26 Mar 2014 13:50:38 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============1231901836== Content-Type: multipart/alternative; boundary="1395867038.21ad7c41.19281"; charset="us-ascii" --1395867038.21ad7c41.19281 Date: Wed, 26 Mar 2014 20:50:38 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" https://bugs.freedesktop.org/show_bug.cgi?id=76564 --- Comment #14 from Alex Deucher --- (In reply to comment #13) > Do the PLL values in the log files I posted indicate a problem, or are they > okay? [drm:radeon_compute_pll_avivo], 14875, pll dividers - fb: 23.8 ref: 2, post 8 [drm:radeon_compute_pll_avivo], 7406, pll dividers - fb: 23.7 ref: 2, post 16 The display pll looks fine to me. The clock formula is: pixel_clock = (reference_frequency * feedback_divider) / (reference_divider * post_divider) The reference frequency is 100 Mhz, so: (100Mhz * 23.8) / (2 * 8) = 148.75Mhz (100Mhz * 23.7) / (2 * 16) = 74.0625Mhz > > How can you see the PLL values fglrx is using? You'd need to dump the PLL registers using radeonreg (http://cgit.freedesktop.org/~airlied/radeontool/). PPLL1 0x400 - ref div - bits 9:0 0x404 - fb div - whole part bits 26:16, fractional part bits 3:0 0x408 - post div - bits 6:0 PPLL2 0x440 - ref div - bits 9:0 0x444 - fb div - whole part bits 26:16, fractional part bits 3:0 0x448 - post div - bits 6:0 e.g., ./radeonreg regmatch 0x400 -- You are receiving this mail because: You are the assignee for the bug. --1395867038.21ad7c41.19281 Date: Wed, 26 Mar 2014 20:50:38 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8"

Comment # 14 on bug 76564 from 
(In reply to comment #13)
> Do the PLL values in the log files I posted indicate a problem, or are they
> okay?

[drm:radeon_compute_pll_avivo], 14875, pll dividers - fb: 23.8 ref: 2, post 8
[drm:radeon_compute_pll_avivo], 7406, pll dividers - fb: 23.7 ref: 2, post 16

The display pll looks fine to me. The clock formula is:

pixel_clock = (reference_frequency * feedback_divider) / (reference_divider *
post_divider)

The reference frequency is 100 Mhz, so:

(100Mhz * 23.8) / (2 * 8) = 148.75Mhz

(100Mhz * 23.7) / (2 * 16) = 74.0625Mhz

> 
> How can you see the PLL values fglrx is using?

You'd need to dump the PLL registers using radeonreg
(http://cgit.freedesktop.org/~airlied/radeontool/).
PPLL1
0x400 - ref div - bits 9:0
0x404 - fb div - whole part bits 26:16, fractional part bits 3:0
0x408 - post div - bits 6:0
PPLL2
0x440 - ref div - bits 9:0
0x444 - fb div - whole part bits 26:16, fractional part bits 3:0
0x448 - post div - bits 6:0

e.g., ./radeonreg regmatch 0x400

You are receiving this mail because:
  • You are the assignee for the bug.
--1395867038.21ad7c41.19281-- --===============1231901836== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel --===============1231901836==--