Commen=
t # 45
on bug 76564<=
/a>
from Christian K=C3=B6nig
(In reply to comment #=
44)
> (In reply to comment #43)
> > We could also update the adjusted mode clock to the actual clock =
set by the
> > pll so that drm_calc_timestamping_constants() uses the actual clo=
ck value on
> > the PLL. E.g.,
> >=20
> > diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
> > b/drivers/gpu/drm/radeon/atombios_crtc.c
> > index daa4dd3..2a2da82 100644
> > --- a/drivers/gpu/drm/radeon/atombios_crtc.c
> > +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
> > @@ -1085,6 +1085,7 @@ static void atombios_crtc_s=
et_pll(struct drm_crtc
> > *crtc, struct drm_display_mode
> > atombios_crtc_program_ss(rdev, ATOM_ENABLE,
> > radeon_crtc->pll_id,
> > radeon_crtc->crtc_id,
> > &radeon_crtc->ss);
> > }
> > + mode->clock =3D pll_clock * 10;
> > }
> >=20=20
> > static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
>=20
> I think that would only help if radeon_compute_pll_avivo could not com=
pute
> an exact match. In the case of 23.976Hz the target clock is 74170kHz a=
nd the
> PLL is set exactly to this value.
> This does raise another question why the target clock' last digit is a=
lways
> zero? For example, for 23.976Hz the target clock should be 74176kHz (w=
ith
> correct rounding). I looked through the source code, but the target cl=
ock
> seems to come all the way from some deep generic drm code.
>=20
> 74176kHz could be matched by the PLL using fb=3D927.2, post_div=3D10 a=
nd
> ref_div=3D125
You might want to take a look at atombios_adjust_pll which does the mode fi=
xup
before a mode is actually used.
Since atombios always works with 10khz pixel clock which always sets the ta=
rget
clocks last digit to zero.