From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 76564] [AMD Fusion E-350] HDMI refresh rates doesn't match expectations Date: Thu, 27 Mar 2014 17:14:31 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1386773222==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 393C36EA16 for ; Thu, 27 Mar 2014 10:14:31 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============1386773222== Content-Type: multipart/alternative; boundary="1395940471.f3b1b50.19415"; charset="us-ascii" --1395940471.f3b1b50.19415 Date: Thu, 27 Mar 2014 17:14:31 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" https://bugs.freedesktop.org/show_bug.cgi?id=76564 --- Comment #15 from jeroen --- (In reply to comment #14) > (In reply to comment #13) > > Do the PLL values in the log files I posted indicate a problem, or are they > > okay? > > [drm:radeon_compute_pll_avivo], 14875, pll dividers - fb: 23.8 ref: 2, post 8 > [drm:radeon_compute_pll_avivo], 7406, pll dividers - fb: 23.7 ref: 2, post 16 > > The display pll looks fine to me. The clock formula is: > > pixel_clock = (reference_frequency * feedback_divider) / (reference_divider > * post_divider) > > The reference frequency is 100 Mhz, so: > > (100Mhz * 23.8) / (2 * 8) = 148.75Mhz > > (100Mhz * 23.7) / (2 * 16) = 74.0625Mhz > > > > > How can you see the PLL values fglrx is using? > > You'd need to dump the PLL registers using radeonreg > (http://cgit.freedesktop.org/~airlied/radeontool/). > PPLL1 > 0x400 - ref div - bits 9:0 > 0x404 - fb div - whole part bits 26:16, fractional part bits 3:0 > 0x408 - post div - bits 6:0 > PPLL2 > 0x440 - ref div - bits 9:0 > 0x444 - fb div - whole part bits 26:16, fractional part bits 3:0 > 0x448 - post div - bits 6:0 > > e.g., ./radeonreg regmatch 0x400 I got the results with fglrx: PPLL1@50Hz: fb=23.7 ref=2 post=6 PPLL2@50Hz: fb=296.16 ref=7 post=6 PPLL1@23.976Hz: fb=23.7 ref=2 post=12 PPLL2@23.976Hz: fb=296.16 ref=7 post=6 PPLL2 does seem to be used as it does not change. PPLL1 has different values than with the radeon OSS driver. What does this mean? -- You are receiving this mail because: You are the assignee for the bug. --1395940471.f3b1b50.19415 Date: Thu, 27 Mar 2014 17:14:31 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8"

Comment # 15 on bug 76564 from 
(In reply to comment #14)
> (In reply to comment #13)
> > Do the PLL values in the log files I posted indicate a problem, or are they
> > okay?
> 
> [drm:radeon_compute_pll_avivo], 14875, pll dividers - fb: 23.8 ref: 2, post 8
> [drm:radeon_compute_pll_avivo], 7406, pll dividers - fb: 23.7 ref: 2, post 16
> 
> The display pll looks fine to me. The clock formula is:
> 
> pixel_clock = (reference_frequency * feedback_divider) / (reference_divider
> * post_divider)
> 
> The reference frequency is 100 Mhz, so:
> 
> (100Mhz * 23.8) / (2 * 8) = 148.75Mhz
> 
> (100Mhz * 23.7) / (2 * 16) = 74.0625Mhz
> 
> > 
> > How can you see the PLL values fglrx is using?
> 
> You'd need to dump the PLL registers using radeonreg
> (http://cgit.freedesktop.org/~airlied/radeontool/).
> PPLL1
> 0x400 - ref div - bits 9:0
> 0x404 - fb div - whole part bits 26:16, fractional part bits 3:0
> 0x408 - post div - bits 6:0
> PPLL2
> 0x440 - ref div - bits 9:0
> 0x444 - fb div - whole part bits 26:16, fractional part bits 3:0
> 0x448 - post div - bits 6:0
> 
> e.g., ./radeonreg regmatch 0x400

I got the results with fglrx:
PPLL1@50Hz:     fb=23.7    ref=2    post=6
PPLL2@50Hz:     fb=296.16  ref=7    post=6
PPLL1@23.976Hz: fb=23.7    ref=2    post=12
PPLL2@23.976Hz: fb=296.16  ref=7    post=6

PPLL2 does seem to be used as it does not change. PPLL1 has different values
than with the radeon OSS driver. What does this mean?

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  • You are the assignee for the bug.
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