From mboxrd@z Thu Jan 1 00:00:00 1970
From: bugzilla-daemon@freedesktop.org
Subject: [Bug 77009] 24P playback video signal loss with latest DRI patches
Date: Mon, 07 Apr 2014 15:45:17 +0000
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Date: Mon, 7 Apr 2014 15:45:17 +0000
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https://bugs.freedesktop.org/show_bug.cgi?id=77009
--- Comment #21 from Garrett ---
Created attachment 97043
--> https://bugs.freedesktop.org/attachment.cgi?id=97043&action=edit
368 and others dmesg
>Garrett, please stop trying to merge the patches. Since the initial change is >already upsteram we are going to need to fix it in a separate patch anyway.
Sorry. New to this FOSS stuff. OE is a complete OS download with local code
not pulling from mainline kernels (from what I can tell). It was tricky for me
to patch it. I am trying to be transparent so others can reproduce my results
easily.
>My fix limited the reference divider so that "post_div * ref_div <= 100". Could >you try to raise the 100 to see at which point your TV says the signal isn't >valid any more?
>With a limit of 500 you should be at the same point as before, so I suggest to >try values of 200, 300, 400 first. Then if 200 works but 300 doesn't (for >example) try 250, and so on...
Thanks for the tips.
OK- I built many. 368 is the closest I got. I have to head to the office. I
uploaded all dmesg, tests. What I don't understand is the pll numbers go up
and down, despite having the higher max vals. This concerns me..
Hope it helps. I assume you do not want to run all pc's at max. Else
tolerances at the hardware/silica/chipset level may result in similar results
to my sys. But at least now I can tune my sys. :)
368 is much higher than 100. LMK if you need more. TIA.
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Date: Mon, 7 Apr 2014 15:45:17 +0000
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Comment # 21
on bug 77009
from Garrett
Created attachment 97043 [details]
368 and others dmesg
>Garrett, please stop trying to merge the patches. Since the initial change is >already upsteram we are going to need to fix it in a separate patch anyway.
Sorry. New to this FOSS stuff. OE is a complete OS download with local code
not pulling from mainline kernels (from what I can tell). It was tricky for me
to patch it. I am trying to be transparent so others can reproduce my results
easily.
>My fix limited the reference divider so that "post_div * ref_div <= 100". Could >you try to raise the 100 to see at which point your TV says the signal isn't >valid any more?
>With a limit of 500 you should be at the same point as before, so I suggest to >try values of 200, 300, 400 first. Then if 200 works but 300 doesn't (for >example) try 250, and so on...
Thanks for the tips.
OK- I built many. 368 is the closest I got. I have to head to the office. I
uploaded all dmesg, tests. What I don't understand is the pll numbers go up
and down, despite having the higher max vals. This concerns me..
Hope it helps. I assume you do not want to run all pc's at max. Else
tolerances at the hardware/silica/chipset level may result in similar results
to my sys. But at least now I can tune my sys. :)
368 is much higher than 100. LMK if you need more. TIA.
You are receiving this mail because:
- You are the assignee for the bug.
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