Comment # 4 on bug 82201 from Kai

Created attachment 104094 [details]
dmesg with radeon.dpm=1 set

Here you go. The last power state entry in dmesg is:
> switching from power state:
>  ui class: performance
>  internal class: none
>  caps: 
>  uvd    vclk: 0 dclk: 0
>          power level 0    sclk: 30000 mclk: 15000 pcie gen: 3 pcie lanes: 16
>          power level 1    sclk: 98000 mclk: 125000 pcie gen: 3 pcie lanes: 16
>  status: c r 
> switching to power state:
>  ui class: performance
>  internal class: none
>  caps: 
>  uvd    vclk: 0 dclk: 0
>          power level 0    sclk: 30000 mclk: 15000 pcie gen: 3 pcie lanes: 16
>          power level 1    sclk: 98000 mclk: 125000 pcie gen: 3 pcie lanes: 16
>  status: c r