From: bugzilla-daemon@freedesktop.org
To: dri-devel@lists.freedesktop.org
Subject: [Bug 84977] New: r300/compiler: register allocation pass generate invalid swizzle for r300/r400
Date: Tue, 14 Oct 2014 08:31:56 +0000 [thread overview]
Message-ID: <bug-84977-502@http.bugs.freedesktop.org/> (raw)
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https://bugs.freedesktop.org/show_bug.cgi?id=84977
Bug ID: 84977
Summary: r300/compiler: register allocation pass generate
invalid swizzle for r300/r400
Product: Mesa
Version: unspecified
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priority: medium
Component: Drivers/Gallium/r300
Assignee: dri-devel@lists.freedesktop.org
Reporter: david.heidelberger@ixit.cz
Created attachment 107808
--> https://bugs.freedesktop.org/attachment.cgi?id=107808&action=edit
r300_deadsource.txt
Error:
Not a native swizzle: 00000fc3
Can be workarounded forcing
diff --git a/src/gallium/drivers/r300/compiler/radeon_pair_regalloc.c
b/src/gallium/drivers/r300/compiler/radeon_pair_regalloc.c
index 14f93fb..5682b55 100644
--- a/src/gallium/drivers/r300/compiler/radeon_pair_regalloc.c
+++ b/src/gallium/drivers/r300/compiler/radeon_pair_regalloc.c
@@ -432,6 +432,8 @@ static enum rc_reg_class variable_get_class(
}
}
+ can_change_writemask = 0;
+
class_index = find_class(classes, writemask,
can_change_writemask ? 3 : 1);
done:
Seems like if "(!r300_swizzle_is_native_basic(new_swizzle)) {"
didn't check this one swizzle (checked by fprintf).
Output from register allocation pass compared with can_change_writemask = 0;
--- r300_regalloc.txt 2014-10-14 01:51:00.813113749 +0200
+++ r300_regalloc-workaround.txt 2014-10-14 01:51:40.207223071 +0200
@@ -10,20 +10,20 @@
DP3, src0.xyz, src0.xyz
DP3 temp[3].w, src0._, src0._
5: src0.xyz = input[3], src0.w = temp[3]
- DP3 temp[7].z, src0.xyz, src0.xyz
+ DP3 temp[8].x, src0.xyz, src0.xyz
RSQ temp[4].w, |src0.w|
- 6: src0.xyz = input[6], src1.xyz = temp[7]
- DP3 temp[7].z, src0.xyz, src0.xyz
- RSQ temp[5].w, |src1.z|
- 7: src0.xyz = input[5], src0.w = temp[3]
+ 6: src0.xyz = input[6], src1.xyz = temp[8]
DP3 temp[8].x, src0.xyz, src0.xyz
+ RSQ temp[5].w, |src1.x|
+ 7: src0.xyz = input[5], src0.w = temp[3]
+ DP3 temp[9].x, src0.xyz, src0.xyz
MAD temp[3].w, -src0.w, src0.1, src0.1
- 8: src0.w = temp[4], src1.xyz = input[4], src2.xyz = temp[8]
+ 8: src0.w = temp[4], src1.xyz = input[4], src2.xyz = temp[9]
MAD temp[4].xyz, src0.www, src1.xyz, src0.000
RSQ temp[4].w, |src2.x|
- 9: src0.xyz = temp[7], src1.xyz = temp[7]
+ 9: src0.xyz = temp[7], src1.xyz = temp[8]
MAD temp[7].xy, src0.xy_, src0.11_, src0.HH_
- RSQ temp[6].w, |src1.z|
+ RSQ temp[6].w, |src1.x|
10: src0.xyz = input[3], src0.w = temp[5], src2.xyz = temp[4]
MAD temp[3].xyz, src0.xyz, src0.www, src2.xyz
11: src0.xyz = input[5], src0.w = temp[4]
@@ -38,10 +38,10 @@
15: src0.xyz = temp[6], src1.xyz = temp[4]
DP3_SAT temp[4].x, src0.xyz, src1.xyz
16: src0.xyz = temp[3]
- DP3 temp[4].y, src0.xyz, src0.xyz
- 17: src0.xyz = temp[5], src1.xyz = const[7], src2.xyz = temp[4]
+ DP3 temp[7].x, src0.xyz, src0.xyz
+ 17: src0.xyz = temp[5], src1.xyz = const[7], src2.xyz = temp[7]
MAD temp[5].xy, src0.xy_, src1.xx_, src1.yy_
- RSQ temp[5].w, |src2.y|
+ RSQ temp[5].w, |src2.x|
18: src0.xyz = temp[4], src0.w = input[0], src1.xyz = input[0]
MAD temp[0].xyz, src0.xxx, src1.xyz, src0.000
MAD temp[0].w, src0.x, src0.w, src0.0
@@ -53,24 +53,24 @@
DP3_SAT, src0.xyz, src1.xyz
DP3_SAT temp[5].w, src0._, src0._
22: src0.xyz = temp[5], src0.w = const[7], src1.xyz = const[7]
- MAD temp[3].x, src0.y__, src1.z__, src0.w__
+ MAD temp[3].z, src0.__y, src1.__z, src0.__w
MAD temp[6].w, src0.x, src1.z, src0.w
23: src0.xyz = temp[5], src0.w = temp[6], src1.xyz = temp[3], src1.w =
const[6]
- MAD temp[3].x, src0.y__, src1.x__, src1.w__
+ MAD temp[3].z, src0.__y, src1.__z, src1.__w
MAD temp[6].w, src0.x, src0.w, src1.w
24: src0.xyz = temp[5], src0.w = temp[6], src1.xyz = temp[3], src2.xyz =
const[8]
- MAD temp[3].x, src0.y__, src1.x__, src2.x__
+ MAD temp[3].z, src0.__y, src1.__z, src2.__x
MAD temp[6].w, src0.x, src0.w, src2.x
25: src0.w = temp[5]
LG2 temp[5].w, src0.w
26: src0.xyz = temp[5], src0.w = temp[6], src1.xyz = temp[3]
- MAD temp[6].x, src0.y__, src1.x__, -src0.H__
+ MAD temp[6].z, src0.__y, src1.__z, -src0.__H
MAD temp[6].w, src0.x, src0.w, -src0.H
27: src0.xyz = temp[5], src0.w = temp[5], src1.xyz = temp[6], src1.w =
temp[6], src2.xyz = const[4]
- MAD temp[3].xy, src0.xy_, src1.wx_, src0.11_
+ MAD temp[3].xy, src0.xy_, src1.wz_, src0.11_
MAD temp[5].w, src0.w, src2.x, src0.0
28: src0.xyz = temp[3], src0.w = temp[4]
- MAD temp[3].x, -src0.x__, src0.1__, src0.y__
+ MAD temp[3].y, -src0._x_, src0._1_, src0._y_
MAD temp[4].w, -src0.x, src0.1, src0.w
29: src0.w = temp[5]
EX2 temp[5].w, src0.w
@@ -78,7 +78,7 @@
MAD temp[1].xyz, src1.www, src1.xyz, src0.000
MAD temp[1].w, src1.w, src0.w, src0.0
31: src0.xyz = temp[3]
- RCP temp[5].w, src0.x
+ RCP temp[5].w, src0.y
32: src0.w = temp[4], src1.w = temp[5]
MAD_SAT temp[4].w, src1.w, src0.w, src0.0
33: src0.xyz = const[8], src0.w = temp[4]
@@ -110,4 +110,4 @@
MAD temp[0].w, src2.w, srcp.w, src0.0
43: src0.xyz = temp[0], src0.w = temp[0]
MAD color[0].xyz, src0.xyz, src0.111, src0.000
- MAD color[0].w, src0.w, src0.1, src0.0
+ MAD color[0].w, src0.w, src0.1, src0.0
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next reply other threads:[~2014-10-14 8:31 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-14 8:31 bugzilla-daemon [this message]
2014-10-14 8:33 ` [Bug 84977] r300/compiler: register allocation pass generate invalid swizzle for r300/r400 bugzilla-daemon
2014-10-14 8:34 ` bugzilla-daemon
2014-10-14 17:07 ` bugzilla-daemon
2014-10-14 22:11 ` bugzilla-daemon
2014-10-15 13:55 ` bugzilla-daemon
2014-10-15 21:51 ` bugzilla-daemon
2014-10-17 14:07 ` bugzilla-daemon
2014-10-18 10:07 ` bugzilla-daemon
2014-10-28 11:02 ` bugzilla-daemon
2014-10-28 11:18 ` bugzilla-daemon
2014-10-28 21:56 ` bugzilla-daemon
2019-09-18 18:52 ` bugzilla-daemon
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