From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 89699] Regression in 10.5.1 causes flickering/artifacting in a particular video game Date: Fri, 17 Jul 2015 21:22:58 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0164095530==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id C409F6ED2C for ; Fri, 17 Jul 2015 14:22:58 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0164095530== Content-Type: multipart/alternative; boundary="1437168178.AB701.25609"; charset="UTF-8" --1437168178.AB701.25609 Date: Fri, 17 Jul 2015 21:22:58 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable https://bugs.freedesktop.org/show_bug.cgi?id=3D89699 --- Comment #21 from Maxqia --- Did some Bisecting and I Got ... 67a77ecdec3ba701eb63783535c43abf6eb1ab29 is the first bad commit commit 67a77ecdec3ba701eb63783535c43abf6eb1ab29 Author: Marek Ol=C5=A1=C3=A1k Date: Sun Jan 4 22:16:53 2015 +0100 radeonsi: don't use TC L2 for updating descriptors on SI It's causing problems, because we mix uncached CP DMA with cached WRITE_DATA when updating the same memory. The solution for SI is to use uncached access here, because CP DMA does= n't support cached access. CIK will be handled in the next patch. Reviewed-by: Michel D=C3=A4nzer :040000 040000 76fed826a37a921280bbb3c30b27921b58a143db 6a5d816cf39df3265bd9a672cecb5ab94ab97195 M src --=20 You are receiving this mail because: You are the assignee for the bug. --1437168178.AB701.25609 Date: Fri, 17 Jul 2015 21:22:58 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Commen= t # 21 on bug 89699<= /a> from Maxqia 
Did some Bisecting and I Got ...

67a77ecdec3ba701eb63783535c43abf6eb1ab29 is the first bad commit
commit 67a77ecdec3ba701eb63783535c43abf6eb1ab29
Author: Marek Ol=C5=A1=C3=A1k <marek.olsak@amd.com>
Date:   Sun Jan 4 22:16:53 2015 +0100

    radeonsi: don't use TC L2 for updating descriptors on SI

    It's causing problems, because we mix uncached CP DMA with cached
WRITE_DATA
    when updating the same memory.

    The solution for SI is to use uncached access here, because CP DMA does=
n't
    support cached access.

    CIK will be handled in the next patch.

    Reviewed-by: Michel D=C3=A4nzer <michel.daenzer@amd.com>

:040000 040000 76fed826a37a921280bbb3c30b27921b58a143db
6a5d816cf39df3265bd9a672cecb5ab94ab97195 M    src

You are receiving this mail because: =20=20=20=20=20=20
  • You are the assignee for the bug.
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