Comment # 5 on bug 91509 from Roland Scheidegger

(In reply to Roland Scheidegger from comment #4)
> As a quick hunch based on your observations and some quick look in the code,
> it seems depth buffers need to be 128 byte aligned on r200 (and 64 byte on
> r100 though that's just based on the tile/untile code), but
> radeon_alloc_renderbuffer_storage() only does it to 64 bytes: (pitch = ((cpp
> * width + 63) & ~63) / cpp;)
> Could you try out if increasing that to 128 byte alignment there would help?
> For the heck of it I can't figure out though from where the window
> depth/colorbuffers get their alignment, so I've no idea how that's
> calculated there...
> Not sure right now on color buffers neither...

Actually if I see that right it looks like the xorg ati driver would align
things to 64 pixels for non-tiled surfaces and 256 / cpp for tiled ones (so
still 64 pixels for z24s8). That would be even twice of what I suggested above.
May not really be required, though. The docs seem to suggest 8 pixels for color
buffers both for r100 and r200 but tile sized if tiling is used (whatever the
tile size is, seems to be small though, clearly this has to be a micro-tile).
Depth buffer though says 8 pixels for r100 (or tile sized if tiling is enabled,
though on some chips you can't even disable it) and 32 pixels for r200 (though
given the tiling code I have some doubts that's enough for z16). In any case
though I stick to my 128byte recommendation for r200 depth buffers...