From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 94012] Tonga OpenCL clpeak vm faults Date: Thu, 31 Mar 2016 15:14:31 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0938000167==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id D20EF6E24D for ; Thu, 31 Mar 2016 15:14:30 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0938000167== Content-Type: multipart/alternative; boundary="14594372700.D52f.31453"; charset="UTF-8" --14594372700.D52f.31453 Date: Thu, 31 Mar 2016 15:14:30 +0000 MIME-Version: 1.0 Content-Type: text/plain https://bugs.freedesktop.org/show_bug.cgi?id=94012 Andy Furniss changed: What |Removed |Added ---------------------------------------------------------------------------- Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #2 from Andy Furniss --- fixed by llvm commit commit d3adac51fcce66e8c79b77299fef9e5f6c4c646e Author: Tom Stellard Date: Wed Mar 30 16:35:09 2016 +0000 AMDGPU/SI: Enable lanemask tracking in misched Summary: This results in higher register usage, but should make it easier for the compiler to hide latency. This pass is a prerequisite for some more scheduler improvements, and I think the increase register usage with this patch is acceptable, because when combined with the scheduler improvements, the total register usage will decrease. shader-db stats: 2382 shaders in 478 tests Totals: SGPRS: 48672 -> 49088 (0.85 %) VGPRS: 34148 -> 34847 (2.05 %) Code Size: 1285816 -> 1289128 (0.26 %) bytes LDS: 28 -> 28 (0.00 %) blocks Scratch: 492544 -> 573440 (16.42 %) bytes per wave Max Waves: 6856 -> 6846 (-0.15 %) Wait states: 0 -> 0 (0.00 %) Depends on D18451 Reviewers: nhaehnle, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18452 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264876 91177308-0d34-0410-b5e6-96231b3b80d8 -- You are receiving this mail because: You are the assignee for the bug. --14594372700.D52f.31453 Date: Thu, 31 Mar 2016 15:14:30 +0000 MIME-Version: 1.0 Content-Type: text/html changed bug 94012
What Removed Added
Resolution --- FIXED
Status NEW RESOLVED

Comment # 2 on bug 94012 from 
fixed by llvm commit

commit d3adac51fcce66e8c79b77299fef9e5f6c4c646e
Author: Tom Stellard <thomas.stellard@amd.com>
Date:   Wed Mar 30 16:35:09 2016 +0000

    AMDGPU/SI: Enable lanemask tracking in misched

    Summary:
    This results in higher register usage, but should make it easier for
    the compiler to hide latency.

    This pass is a prerequisite for some more scheduler improvements, and I
    think the increase register usage with this patch is acceptable, because
    when combined with the scheduler improvements, the total register usage
    will decrease.

    shader-db stats:

    2382 shaders in 478 tests
    Totals:
    SGPRS: 48672 -> 49088 (0.85 %)
    VGPRS: 34148 -> 34847 (2.05 %)
    Code Size: 1285816 -> 1289128 (0.26 %) bytes
    LDS: 28 -> 28 (0.00 %) blocks
    Scratch: 492544 -> 573440 (16.42 %) bytes per wave
    Max Waves: 6856 -> 6846 (-0.15 %)
    Wait states: 0 -> 0 (0.00 %)

    Depends on D18451

    Reviewers: nhaehnle, arsenm

    Subscribers: arsenm, llvm-commits

    Differential Revision: http://reviews.llvm.org/D18452

    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264876
91177308-0d34-0410-b5e6-96231b3b80d8

You are receiving this mail because:
  • You are the assignee for the bug.
--14594372700.D52f.31453-- --===============0938000167== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== --===============0938000167==--