From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 94445] Tonga llvm assert since RegisterCoalescer: Need to check DstReg+SrcReg for missing undef flags Date: Thu, 31 Mar 2016 15:13:12 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0829259433==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [IPv6:2610:10:20:722:a800:ff:fe98:4b55]) by gabe.freedesktop.org (Postfix) with ESMTP id C7C9D6E24F for ; Thu, 31 Mar 2016 15:13:11 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0829259433== Content-Type: multipart/alternative; boundary="14594371911.74Bb1.30334"; charset="UTF-8" --14594371911.74Bb1.30334 Date: Thu, 31 Mar 2016 15:13:11 +0000 MIME-Version: 1.0 Content-Type: text/plain https://bugs.freedesktop.org/show_bug.cgi?id=94445 --- Comment #8 from Andy Furniss --- Fixing commit = commit d3adac51fcce66e8c79b77299fef9e5f6c4c646e Author: Tom Stellard Date: Wed Mar 30 16:35:09 2016 +0000 AMDGPU/SI: Enable lanemask tracking in misched Summary: This results in higher register usage, but should make it easier for the compiler to hide latency. This pass is a prerequisite for some more scheduler improvements, and I think the increase register usage with this patch is acceptable, because when combined with the scheduler improvements, the total register usage will decrease. shader-db stats: 2382 shaders in 478 tests Totals: SGPRS: 48672 -> 49088 (0.85 %) VGPRS: 34148 -> 34847 (2.05 %) Code Size: 1285816 -> 1289128 (0.26 %) bytes LDS: 28 -> 28 (0.00 %) blocks Scratch: 492544 -> 573440 (16.42 %) bytes per wave Max Waves: 6856 -> 6846 (-0.15 %) Wait states: 0 -> 0 (0.00 %) Depends on D18451 Reviewers: nhaehnle, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18452 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264876 91177308-0d34-0410-b5e6-96231b3b80d8 -- You are receiving this mail because: You are the assignee for the bug. --14594371911.74Bb1.30334 Date: Thu, 31 Mar 2016 15:13:11 +0000 MIME-Version: 1.0 Content-Type: text/html

Comment # 8 on bug 94445 from 
Fixing commit = 

commit d3adac51fcce66e8c79b77299fef9e5f6c4c646e
Author: Tom Stellard <thomas.stellard@amd.com>
Date:   Wed Mar 30 16:35:09 2016 +0000

    AMDGPU/SI: Enable lanemask tracking in misched

    Summary:
    This results in higher register usage, but should make it easier for
    the compiler to hide latency.

    This pass is a prerequisite for some more scheduler improvements, and I
    think the increase register usage with this patch is acceptable, because
    when combined with the scheduler improvements, the total register usage
    will decrease.

    shader-db stats:

    2382 shaders in 478 tests
    Totals:
    SGPRS: 48672 -> 49088 (0.85 %)
    VGPRS: 34148 -> 34847 (2.05 %)
    Code Size: 1285816 -> 1289128 (0.26 %) bytes
    LDS: 28 -> 28 (0.00 %) blocks
    Scratch: 492544 -> 573440 (16.42 %) bytes per wave
    Max Waves: 6856 -> 6846 (-0.15 %)
    Wait states: 0 -> 0 (0.00 %)

    Depends on D18451

    Reviewers: nhaehnle, arsenm

    Subscribers: arsenm, llvm-commits

    Differential Revision: http://reviews.llvm.org/D18452

    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264876
91177308-0d34-0410-b5e6-96231b3b80d8

You are receiving this mail because:
  • You are the assignee for the bug.
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