From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 96326] Heavy screen flickering in OpenGL apps on R9 390 Date: Mon, 01 Aug 2016 14:04:10 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0636522382==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 16028880B0 for ; Mon, 1 Aug 2016 14:04:10 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0636522382== Content-Type: multipart/alternative; boundary="14700602500.220daE7A.12707"; charset="UTF-8" --14700602500.220daE7A.12707 Date: Mon, 1 Aug 2016 14:04:10 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated https://bugs.freedesktop.org/show_bug.cgi?id=3D96326 --- Comment #8 from Jan Ziak <0xe2.0x9a.0x9b@gmail.com> --- (In reply to Alex Deucher from comment #7) > (In reply to Jan Ziak from comment #6) > > (In reply to Alex Deucher from comment #3) > > > Please attach your xorg log and dmesg output. > >=20 > > Upstream Linux kernel does not support variable mclk on R9 390. I enabl= ed > > variable mclk by patching some code in drivers/gpu/drm/amd/amdgpu/ (mos= tly > > ci_dpm.c). >=20 > What patch(es) did you use? I added a function based on ci_dpm_force_state_mclk() in ci_dpm.c. mask is 0x3. ---- static int ci_dpm_force_state_mclk_mask(struct amdgpu_device *adev, u32 mas= k) { struct ci_power_info *pi =3D ci_get_pi(adev); if (!pi->mclk_dpm_key_disabled) { PPSMC_Result smc_result =3D amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, mask); printk("[atomsymbol] %s:%d: mask=3D0x%X, ok=3D%d\n", __FUNCTION= __, __LINE__, mask, smc_result =3D=3D PPSMC_Result_OK); if (smc_result !=3D PPSMC_Result_OK) return -EINVAL; } return 0; } ---- /sys/class/drm/card?/device/power_dpm_force_performance_level is set to "au= to". --=20 You are receiving this mail because: You are the assignee for the bug.= --14700602500.220daE7A.12707 Date: Mon, 1 Aug 2016 14:04:10 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated

Comment= # 8 on bug 96326<= /a> from Jan Ziak
(In reply to Alex Deucher from comment #7)
> (In reply to Jan Ziak from comment #6)
> > (In reply to Alex Deucher from comment #3)
> > > Please attach your xorg log and dmesg output.
> >=20
> > Upstream Linux kernel does not support variable mclk on R9 390. I=
 enabled
> > variable mclk by patching some code in drivers/gpu/drm/amd/amdgpu=
/ (mostly
> > ci_dpm.c).
>=20
> What patch(es) did you use?

I added a function based on ci_dpm_force_state_mclk() in ci_dpm.c.

mask is 0x3.

----
static int ci_dpm_force_state_mclk_mask(struct amdgpu_device *adev, u32 mas=
k) {
    struct ci_power_info *pi =3D ci_get_pi(adev);

    if (!pi->mclk_dpm_key_disabled) {
        PPSMC_Result smc_result =3D
amdgpu_ci_send_msg_to_smc_with_parameter(adev,
PPSMC_MSG_MCLKDPM_SetEnabledMask, mask);
            printk("[atomsymbol] %s:%d: mask=3D0x%X, ok=3D%d\n", =
__FUNCTION__,
__LINE__, mask, smc_result =3D=3D PPSMC_Result_OK);
            if (smc_result !=3D PPSMC_Result_OK)
                return -EINVAL;
    }
    return 0;
}
----

/sys/class/drm/card?/device/power_dpm_force_performance_level is set to &qu=
ot;auto".


You are receiving this mail because:
  • You are the assignee for the bug.
= --14700602500.220daE7A.12707-- --===============0636522382== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== --===============0636522382==--