From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 97305] Wrong values returned by GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT & GL_TEXTURE_BUFFER_OFFSET_ALIGNMENT randomly breaks stuff Date: Thu, 11 Aug 2016 22:18:38 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1101790741==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 1E2546EA0D for ; Thu, 11 Aug 2016 22:18:38 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============1101790741== Content-Type: multipart/alternative; boundary="14709539180.24ad0.5215"; charset="UTF-8" --14709539180.24ad0.5215 Date: Thu, 11 Aug 2016 22:18:38 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated https://bugs.freedesktop.org/show_bug.cgi?id=3D97305 --- Comment #6 from Matias N. Goldberg --- I'm back. I only tested texture and uniform buffers, not SSBOs. Results: * Setting UBOs to 4 byte alignments didn't seem to matter in any way. Performance didn't seem to be affected either. Nonetheless given that AMD always sets it to 256; this is what I'd recommend (i.e. there could be undocumented hw errors for edge cases?) * Setting TBOs to non-16 byte alignments breaks in a specific pattern (i.e.= 4 byte alignments produce certain glitches, 8 byte alignments produce a diffe= rent set of glitches, 12 byte alignments a different set, etc). Setting TBOs to = 16 byte alignments fixes everything. I benchmarked 256-byte alignments vs 16-b= yte alignments-non-256-byte and couldn't see any performance difference (the sa= mple kept around 46.50-47.00ms all the time). --=20 You are receiving this mail because: You are the assignee for the bug.= --14709539180.24ad0.5215 Date: Thu, 11 Aug 2016 22:18:38 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated

Comment= # 6 on bug 97305<= /a> from Matias N. Goldberg 
I'm back.

I only tested texture and uniform buffers, not SSBOs.

Results:
* Setting UBOs to 4 byte alignments didn't seem to matter in any way.
Performance didn't seem to be affected either. Nonetheless given that AMD
always sets it to 256; this is what I'd recommend (i.e. there could be
undocumented hw errors for edge cases?)

* Setting TBOs to non-16 byte alignments breaks in a specific pattern (i.e.=
 4
byte alignments produce certain glitches, 8 byte alignments produce a diffe=
rent
set of glitches, 12 byte alignments a different set, etc). Setting TBOs to =
16
byte alignments fixes everything. I benchmarked 256-byte alignments vs 16-b=
yte
alignments-non-256-byte and couldn't see any performance difference (the sa=
mple
kept around 46.50-47.00ms all the time).

You are receiving this mail because:
  • You are the assignee for the bug.
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