From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 98761] [regression][radeonsi][polaris]"radeonsi: set IF_THRESHOLD to 3" breaks Witcher2's ground Date: Mon, 21 Nov 2016 23:52:43 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0488769212==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 662B56E623 for ; Mon, 21 Nov 2016 23:52:43 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0488769212== Content-Type: multipart/alternative; boundary="14797723633.CE33a4aC.7613"; charset="UTF-8" --14797723633.CE33a4aC.7613 Date: Mon, 21 Nov 2016 23:52:43 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated https://bugs.freedesktop.org/show_bug.cgi?id=3D98761 --- Comment #11 from Marek Ol=C5=A1=C3=A1k --- First bad commit: commit 4404d0d6e354e80dd7f8f0a0e12d8ad809cf007e Author: Matt Arsenault Date: Sun Nov 13 18:20:54 2016 +0000 AMDGPU: Implement SGPR spilling with scalar stores nThis avoids the nasty problems caused by using memory instructions that read the exec mask while spilling / restoring registers used for control flow masking, but only for VI when these were added. This always uses the scalar stores when enabled currently, but it may be better to still try to spill to a VGPR and use this on the fallback memory path. The cache also needs to be flushed before wave termination if a scalar store is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286766 91177308-0d34-0410-b5e6-96231b3b80d8 --=20 You are receiving this mail because: You are the assignee for the bug.= --14797723633.CE33a4aC.7613 Date: Mon, 21 Nov 2016 23:52:43 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated

Commen= t # 11 on bug 98761<= /a> from Marek Ol=C5=A1=C3=A1k 
First bad commit:

commit 4404d0d6e354e80dd7f8f0a0e12d8ad809cf007e
Author: Matt Arsenault <Matthew.Arsenault@amd.com>
Date:   Sun Nov 13 18:20:54 2016 +0000

    AMDGPU: Implement SGPR spilling with scalar stores

    nThis avoids the nasty problems caused by using
    memory instructions that read the exec mask while
    spilling / restoring registers used for control flow
    masking, but only for VI when these were added.

    This always uses the scalar stores when enabled currently,
    but it may be better to still try to spill to a VGPR
    and use this on the fallback memory path.

    The cache also needs to be flushed before wave termination
    if a scalar store is used.

    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286766
91177308-0d34-0410-b5e6-96231b3b80d8

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