[Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state

[bugzilla-daemon@freedesktop.org]

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https://bugs.freedesktop.org/show_bug.cgi?id=98821

--- Comment #8 from Alex Deucher <alexdeucher@gmail.com> ---
(In reply to Arek Ruśniak from comment #7)
> Alex I use something like that:
> watch -n 1 -c "cat /sys/kernel/debug/dri/0/amdgpu_pm_info"
> combined with 
> vblank_mode=0 glxgears
> it should set mclk on fire IIRC, but it was still 300MHz, bisecting gives me:
> https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.10-
> wip&id=ddfe1db18752b08d88d81cb7b661e1f982fc5d04
> 


I doubt regular sized gears will generate enough memory load to raise the mclk.
 Does it work if you try:
vblank_mode=0 glxgears -fullscreen
Or try some more demanding app.

> but when I've tested (in the bisecting proces) commit [1] I saw that mclk i
> set always on 2000MHz... and this is first commit (I checked +/- 1) when is
> set on HIGH no matter what.
> 
> So yes, this are two issues in one I believe because revert
> 1b7eab1f8346ab3b8e4fc54882306340a84497a8 fixes them all.

Also does the number of displays attached change the behavior?  When you say
fix, do you mean mclk stays high, or changes dynamically?

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