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Mon, 27 Apr 2026 07:35:14 +0000 Message-ID: Date: Mon, 27 Apr 2026 09:35:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH for drm-misc-fixes v5 4/4] drm/hisilicon/hibmc: use clock to look up the PLL value To: Yongbang Shi , dmitry.baryshkov@oss.qualcomm.com, tiantao6@hisilicon.com, xinliang.liu@linaro.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, airlied@gmail.com, daniel@ffwll.ch, kong.kongxinwei@hisilicon.com Cc: liangjian010@huawei.com, chenjianmin@huawei.com, fengsheng5@huawei.com, helin52@h-partners.com, shenjian15@huawei.com, shaojijie@huawei.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20260423063233.1267631-1-shiyongbang@huawei.com> <20260423063233.1267631-5-shiyongbang@huawei.com> Content-Language: en-US From: Thomas Zimmermann Autocrypt: addr=tzimmermann@suse.de; keydata= xsBNBFs50uABCADEHPidWt974CaxBVbrIBwqcq/WURinJ3+2WlIrKWspiP83vfZKaXhFYsdg XH47fDVbPPj+d6tQrw5lPQCyqjwrCPYnq3WlIBnGPJ4/jreTL6V+qfKRDlGLWFjZcsrPJGE0 BeB5BbqP5erN1qylK9i3gPoQjXGhpBpQYwRrEyQyjuvk+Ev0K1Jc5tVDeJAuau3TGNgah4Yc hdHm3bkPjz9EErV85RwvImQ1dptvx6s7xzwXTgGAsaYZsL8WCwDaTuqFa1d1jjlaxg6+tZsB 9GluwvIhSezPgnEmimZDkGnZRRSFiGP8yjqTjjWuf0bSj5rUnTGiyLyRZRNGcXmu6hjlABEB AAHNJ1Rob21hcyBaaW1tZXJtYW5uIDx0emltbWVybWFubkBzdXNlLmRlPsLAjgQTAQgAOAIb AwULCQgHAgYVCgkICwIEFgIDAQIeAQIXgBYhBHIX+6yM6c9jRKFo5WgNwR1TC3ojBQJftODH AAoJEGgNwR1TC3ojx1wH/0hKGWugiqDgLNXLRD/4TfHBEKmxIrmfu9Z5t7vwUKfwhFL6hqvo lXPJJKQpQ2z8+X2vZm/slsLn7J1yjrOsoJhKABDi+3QWWSGkaGwRJAdPVVyJMfJRNNNIKwVb U6B1BkX2XDKDGffF4TxlOpSQzdtNI/9gleOoUA8+jy8knnDYzjBNOZqLG2FuTdicBXblz0Mf vg41gd9kCwYXDnD91rJU8tzylXv03E75NCaTxTM+FBXPmsAVYQ4GYhhgFt8S2UWMoaaABLDe 7l5FdnLdDEcbmd8uLU2CaG4W2cLrUaI4jz2XbkcPQkqTQ3EB67hYkjiEE6Zy3ggOitiQGcqp j//OwE0EWznS4AEIAMYmP4M/V+T5RY5at/g7rUdNsLhWv1APYrh9RQefODYHrNRHUE9eosYb T6XMryR9hT8XlGOYRwKWwiQBoWSDiTMo/Xi29jUnn4BXfI2px2DTXwc22LKtLAgTRjP+qbU6 3Y0xnQN29UGDbYgyyK51DW3H0If2a3JNsheAAK+Xc9baj0LGIc8T9uiEWHBnCH+RdhgATnWW GKdDegUR5BkDfDg5O/FISymJBHx2Dyoklv5g4BzkgqTqwmaYzsl8UxZKvbaxq0zbehDda8lv hFXodNFMAgTLJlLuDYOGLK2AwbrS3Sp0AEbkpdJBb44qVlGm5bApZouHeJ/+n+7r12+lqdsA EQEAAcLAdgQYAQgAIAIbDBYhBHIX+6yM6c9jRKFo5WgNwR1TC3ojBQJftOH6AAoJEGgNwR1T C3ojVSkIALpAPkIJPQoURPb1VWjh34l0HlglmYHvZszJWTXYwavHR8+k6Baa6H7ufXNQtThR yIxJrQLW6rV5lm7TjhffEhxVCn37+cg0zZ3j7zIsSS0rx/aMwi6VhFJA5hfn3T0TtrijKP4A SAQO9xD1Zk9/61JWk8OysuIh7MXkl0fxbRKWE93XeQBhIJHQfnc+YBLprdnxR446Sh8Wn/2D Ya8cavuWf2zrB6cZurs048xe0UbSW5AOSo4V9M0jzYI4nZqTmPxYyXbm30Kvmz0rYVRaitYJ 4kyYYMhuULvrJDMjZRvaNe52tkKAvMevcGdt38H4KSVXAylqyQOW5zvPc4/sq9c= In-Reply-To: <20260423063233.1267631-5-shiyongbang@huawei.com> Content-Type: text/plain; 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RCVD_COUNT_TWO(0.00)[2]; MID_RHS_MATCH_FROM(0.00)[]; DNSWL_BLOCKED(0.00)[2a07:de40:b281:106:10:150:64:167:received]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:url, hisilicon.com:email, imap1.dmz-prg2.suse.org:helo, imap1.dmz-prg2.suse.org:rdns, suse.de:dkim, suse.de:mid, huawei.com:email] X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Queue-Id: 180B65BD0A X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Am 23.04.26 um 08:32 schrieb Yongbang Shi: > From: Lin He > > In the past, we use width and height to look up our PLL value. > But actually the actual clock check is also necessnary. There are > some resolutions that width and height same, but its clock different. > Add the clock check when using pll_table to determine the PLL value. > > Fixes: da52605eea8f ("drm/hisilicon/hibmc: Add support for display engine") > Signed-off-by: Lin He > Signed-off-by: Yongbang Shi > --- > ChangeLog: > v2 -> v3: > - remove unused macro CLOCK_TOLERANCE. > v1 -> v2: > - remove tag "Reviewed-by: Tao Tian ", witch will > be given in public. > - add 'drm-misc-fixes' in subject prefix. > --- > .../gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 78 +++++++++++-------- > 1 file changed, 44 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c > index 89bed78f1466..1a07e8146eee 100644 > --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c > +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c > @@ -32,26 +32,43 @@ struct hibmc_display_panel_pll { > struct hibmc_dislay_pll_config { > u64 hdisplay; > u64 vdisplay; > + int clock; > u32 pll1_config_value; > u32 pll2_config_value; > }; > > static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { > - {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, > - {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, > - {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, > - {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, > - {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, > - {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, > - {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > - {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > - {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, > - {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > - {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, > - {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, > - {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, > + {640, 480, 25000, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, > + {800, 600, 40000, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, > + {1024, 768, 65000, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, > + {1152, 864, 78750, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, > + {1280, 768, 80000, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, > + {1280, 720, 74375, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, > + {1280, 960, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > + {1280, 1024, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > + {1440, 900, 105952, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, > + {1600, 900, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > + {1600, 1200, 162500, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, > + {1920, 1080, 148750, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, > + {1920, 1200, 193750, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, > }; > > +static int hibmc_get_best_clock_idx(const struct drm_display_mode *mode) > +{ > + int i, diff; > + > + for (i = 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { > + if (hibmc_pll_table[i].hdisplay == mode->hdisplay && > + hibmc_pll_table[i].vdisplay == mode->vdisplay) { > + diff = abs(mode->clock - hibmc_pll_table[i].clock); > + if (diff < mode->clock / 100) /* tolerance 1/100 */ > + return i; > + } > + } > + > + return -EOPNOTSUPP; This errno code is for sockets. Rather return -MODE_CLOCK_RANGE here, which you can then return from .mode_valid as well. Best regards Thomas > +} > + > static int hibmc_plane_atomic_check(struct drm_plane *plane, > struct drm_atomic_state *state) > { > @@ -214,17 +231,13 @@ static enum drm_mode_status > hibmc_crtc_mode_valid(struct drm_crtc *crtc, > const struct drm_display_mode *mode) > { > - size_t i = 0; > int vrefresh = drm_mode_vrefresh(mode); > > if (vrefresh < 59 || vrefresh > 61) > return MODE_NOCLOCK; > > - for (i = 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { > - if (hibmc_pll_table[i].hdisplay == mode->hdisplay && > - hibmc_pll_table[i].vdisplay == mode->vdisplay) > - return MODE_OK; > - } > + if (hibmc_get_best_clock_idx(mode) >= 0) > + return MODE_OK; > > return MODE_BAD; > } > @@ -281,23 +294,20 @@ static void set_vclock_hisilicon(struct drm_device *dev, u64 pll) > writel(val, priv->mmio + CRT_PLL1_HS); > } > > -static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) > +static void get_pll_config(struct drm_display_mode *mode, u32 *pll1, u32 *pll2) > { > - size_t i; > - size_t count = ARRAY_SIZE(hibmc_pll_table); > - > - for (i = 0; i < count; i++) { > - if (hibmc_pll_table[i].hdisplay == x && > - hibmc_pll_table[i].vdisplay == y) { > - *pll1 = hibmc_pll_table[i].pll1_config_value; > - *pll2 = hibmc_pll_table[i].pll2_config_value; > - return; > - } > + int idx; > + > + idx = hibmc_get_best_clock_idx(mode); > + if (idx < 0) { > + /* if found none, we use default value */ > + *pll1 = CRT_PLL1_HS_25MHZ; > + *pll2 = CRT_PLL2_HS_25MHZ; > + return; > } > > - /* if found none, we use default value */ > - *pll1 = CRT_PLL1_HS_25MHZ; > - *pll2 = CRT_PLL2_HS_25MHZ; > + *pll1 = hibmc_pll_table[idx].pll1_config_value; > + *pll2 = hibmc_pll_table[idx].pll2_config_value; > } > > /* > @@ -319,7 +329,7 @@ static u32 display_ctrl_adjust(struct drm_device *dev, > x = mode->hdisplay; > y = mode->vdisplay; > > - get_pll_config(x, y, &pll1, &pll2); > + get_pll_config(mode, &pll1, &pll2); > writel(pll2, priv->mmio + CRT_PLL2_HS); > set_vclock_hisilicon(dev, pll1); > -- -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstr. 146, 90461 Nürnberg, Germany, www.suse.com GF: Jochen Jaser, Andrew McDonald, Werner Knoblich, (HRB 36809, AG Nürnberg)