[PATCH v3 0/5] drm/omap: Remove CONFIG_DRM_OMAP_NUM_CRTCS and cleanup

[PATCH v3 0/5] drm/omap: Remove CONFIG_DRM_OMAP_NUM_CRTCS and cleanup

[Jyri Sarha]

The first patch removes CONFIG_DRM_OMAP_NUM_CRTCS config option. The
patches number 2-4 gets rid of annoying name collision between dss
backend and omapdrm. The last patch cleans up the unnecessary
complexity from omap_modeset_init().

Changes since v2:
- drm/omap: Get rid of DRM_OMAP_NUM_CRTCS config option
  - No change
- Added:
  - drm/omap: Rename enum omap_plane to enum omap_plane_id
  - drm/omap: Fix ugliest indentation style breaks from previous patch
  - drm/omap: Remove the obsolete #define omap_plane _omap_plane hack
- drm/omap: Major omap_modeset_init() cleanup
  - use memset() to reset omap_crtcs[] in omap_crtc_pre_init()
  - make the mapping between omapdrm plane index and dss plane id explicit

Changes since first version:
- drm/omapdrm: Get rid of DRM_OMAP_NUM_CRTCS config option
  - drm/omapdrm: -> drm/omap:
- Drop:
  - drm/omapdrm: Change possible_crtcs to possible_crtcs_for_planes
  - drm/omapdrm: Separate ids for planes and CRTCs in omap_modeset_init()
- Add:
  - drm/omap: Major omap_modeset_init() cleanup

Jyri Sarha (5):
  drm/omap: Get rid of DRM_OMAP_NUM_CRTCS config option
  drm/omap: Rename enum omap_plane to enum omap_plane_id
  drm/omap: Fix ugliest indentation style breaks from previous patch
  drm/omap: Remove the obsolete #define omap_plane _omap_plane hack
  drm/omap: Major omap_modeset_init() cleanup

 drivers/gpu/drm/omapdrm/Kconfig            |   9 --
 drivers/gpu/drm/omapdrm/dss/dispc.c        | 121 ++++++++--------
 drivers/gpu/drm/omapdrm/dss/dispc.h        |  62 ++++-----
 drivers/gpu/drm/omapdrm/dss/dss.h          |   5 +-
 drivers/gpu/drm/omapdrm/dss/dss_features.c |   6 +-
 drivers/gpu/drm/omapdrm/dss/dss_features.h |   4 +-
 drivers/gpu/drm/omapdrm/dss/omapdss.h      |  15 +-
 drivers/gpu/drm/omapdrm/omap_crtc.c        |  20 ++-
 drivers/gpu/drm/omapdrm/omap_drv.c         | 212 +++++++----------------------
 drivers/gpu/drm/omapdrm/omap_drv.h         |   4 +-
 drivers/gpu/drm/omapdrm/omap_plane.c       |  32 +++--
 11 files changed, 204 insertions(+), 286 deletions(-)

-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v3 1/5] drm/omap: Get rid of DRM_OMAP_NUM_CRTCS config option

[Jyri Sarha]

Allocate one CRTC for each connected output and get rid of
DRM_OMAP_NUM_CRTCS config option. We still can not create more CRTCs
than we have DSS display managers. We also reserve one overlay per
CRTC for primary plane so we can not have more CRTCs than we have
overlays either.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/gpu/drm/omapdrm/Kconfig    |  9 ------
 drivers/gpu/drm/omapdrm/omap_drv.c | 59 +++++++++++---------------------------
 2 files changed, 16 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/Kconfig b/drivers/gpu/drm/omapdrm/Kconfig
index 556f81f..b3d08c5 100644
--- a/drivers/gpu/drm/omapdrm/Kconfig
+++ b/drivers/gpu/drm/omapdrm/Kconfig
@@ -10,15 +10,6 @@ config DRM_OMAP
 
 if DRM_OMAP
 
-config DRM_OMAP_NUM_CRTCS
-	int "Number of CRTCs"
-	range 1 10
-	default 1  if ARCH_OMAP2 || ARCH_OMAP3
-	default 2  if ARCH_OMAP4
-	help
-	  Select the number of video overlays which can be used as framebuffers.
-	  The remaining overlays are reserved for video.
-
 source "drivers/gpu/drm/omapdrm/dss/Kconfig"
 source "drivers/gpu/drm/omapdrm/displays/Kconfig"
 
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index 79a4aad..17c40aa 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -34,11 +34,6 @@
 #define DRIVER_MINOR		0
 #define DRIVER_PATCHLEVEL	0
 
-static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS;
-
-MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs");
-module_param(num_crtc, int, 0600);
-
 /*
  * mode config funcs
  */
@@ -322,7 +317,7 @@ static int omap_modeset_init(struct drm_device *dev)
 	struct omap_dss_device *dssdev = NULL;
 	int num_ovls = dss_feat_get_num_ovls();
 	int num_mgrs = dss_feat_get_num_mgrs();
-	int num_crtcs;
+	int num_crtcs = 0;
 	int i, id = 0;
 	int ret;
 	u32 possible_crtcs;
@@ -334,12 +329,15 @@ static int omap_modeset_init(struct drm_device *dev)
 		return ret;
 
 	/*
-	 * We usually don't want to create a CRTC for each manager, at least
-	 * not until we have a way to expose private planes to userspace.
-	 * Otherwise there would not be enough video pipes left for drm planes.
-	 * We use the num_crtc argument to limit the number of crtcs we create.
+	 * Let's create one CRTC for each connected DSS device if we
+	 * have display managers and overlays (for primary planes) for
+	 * them.
 	 */
-	num_crtcs = min3(num_crtc, num_mgrs, num_ovls);
+	for_each_dss_dev(dssdev)
+		if (omapdss_device_is_connected(dssdev))
+			num_crtcs++;
+
+	num_crtcs = min3(num_crtcs, num_mgrs, num_ovls);
 	possible_crtcs = (1 << num_crtcs) - 1;
 
 	dssdev = NULL;
@@ -379,11 +377,9 @@ static int omap_modeset_init(struct drm_device *dev)
 		drm_mode_connector_attach_encoder(connector, encoder);
 
 		/*
-		 * if we have reached the limit of the crtcs we are allowed to
-		 * create, let's not try to look for a crtc for this
-		 * panel/encoder and onwards, we will, of course, populate the
-		 * the possible_crtcs field for all the encoders with the final
-		 * set of crtcs we create
+		 * if we have reached the limit of the crtcs we can
+		 * create, let's not try to create a crtc for this
+		 * panel/encoder and onwards.
 		 */
 		if (id == num_crtcs)
 			continue;
@@ -418,33 +414,6 @@ static int omap_modeset_init(struct drm_device *dev)
 	}
 
 	/*
-	 * we have allocated crtcs according to the need of the panels/encoders,
-	 * adding more crtcs here if needed
-	 */
-	for (; id < num_crtcs; id++) {
-
-		/* find a free manager for this crtc */
-		for (i = 0; i < num_mgrs; i++) {
-			if (!channel_used(dev, i))
-				break;
-		}
-
-		if (i == num_mgrs) {
-			/* this shouldn't really happen */
-			dev_err(dev->dev, "no managers left for crtc\n");
-			return -ENOMEM;
-		}
-
-		ret = omap_modeset_create_crtc(dev, id, i,
-			possible_crtcs);
-		if (ret < 0) {
-			dev_err(dev->dev,
-				"could not create CRTC (channel %u)\n", i);
-			return ret;
-		}
-	}
-
-	/*
 	 * Create normal planes for the remaining overlays:
 	 */
 	for (; id < num_ovls; id++) {
@@ -459,6 +428,10 @@ static int omap_modeset_init(struct drm_device *dev)
 		priv->planes[priv->num_planes++] = plane;
 	}
 
+	/*
+	 * populate the the possible_crtcs field for all the encoders
+	 * we created.
+	 */
 	for (i = 0; i < priv->num_encoders; i++) {
 		struct drm_encoder *encoder = priv->encoders[i];
 		struct omap_dss_device *dssdev =
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v3 2/5] drm/omap: Rename enum omap_plane to enum omap_plane_id

[Jyri Sarha]

The enum omap_plane conflicted with the same struct name for omapdrm
plane private data. This rename should solve the conflict.

The rename was implement with this very simple coccinelle patch:
------------------------
@@
@@
enum
-omap_plane
+omap_plane_id
------------------------
The patch was applied like this:
spatch --sp-file <cocci_file> --all-includes --in-place --dir drivers/gpu/drm/omapdrm

The above patch did not rename the actual enum definition. That was
added manually on top of the spatch changes.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/gpu/drm/omapdrm/dss/dispc.c        | 122 ++++++++++++++++-------------
 drivers/gpu/drm/omapdrm/dss/dispc.h        |  62 +++++++--------
 drivers/gpu/drm/omapdrm/dss/dss.h          |   5 +-
 drivers/gpu/drm/omapdrm/dss/dss_features.c |   6 +-
 drivers/gpu/drm/omapdrm/dss/dss_features.h |   4 +-
 drivers/gpu/drm/omapdrm/dss/omapdss.h      |  15 ++--
 6 files changed, 114 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index d956e626..17712a3 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -303,8 +303,8 @@ struct color_conv_coef {
 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 
-static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
-static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
+static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane);
+static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane);
 
 static inline void dispc_write_reg(const u16 idx, u32 val)
 {
@@ -657,7 +657,7 @@ bool dispc_wb_go_busy(void)
 
 void dispc_wb_go(void)
 {
-	enum omap_plane plane = OMAP_DSS_WB;
+	enum omap_plane_id plane = OMAP_DSS_WB;
 	bool enable, go;
 
 	enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
@@ -674,29 +674,33 @@ void dispc_wb_go(void)
 	REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 }
 
-static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
+static void dispc_ovl_write_firh_reg(enum omap_plane_id plane, int reg,
+				     u32 value)
 {
 	dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 }
 
-static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
+static void dispc_ovl_write_firhv_reg(enum omap_plane_id plane, int reg,
+				      u32 value)
 {
 	dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 }
 
-static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
+static void dispc_ovl_write_firv_reg(enum omap_plane_id plane, int reg,
+				     u32 value)
 {
 	dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 }
 
-static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
+static void dispc_ovl_write_firh2_reg(enum omap_plane_id plane, int reg,
+				      u32 value)
 {
 	BUG_ON(plane == OMAP_DSS_GFX);
 
 	dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 }
 
-static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
+static void dispc_ovl_write_firhv2_reg(enum omap_plane_id plane, int reg,
 		u32 value)
 {
 	BUG_ON(plane == OMAP_DSS_GFX);
@@ -704,14 +708,15 @@ static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 	dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 }
 
-static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
+static void dispc_ovl_write_firv2_reg(enum omap_plane_id plane, int reg,
+				      u32 value)
 {
 	BUG_ON(plane == OMAP_DSS_GFX);
 
 	dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 }
 
-static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
+static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc,
 				int fir_vinc, int five_taps,
 				enum omap_color_component color_comp)
 {
@@ -757,7 +762,7 @@ static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 }
 
 
-static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
+static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane,
 		const struct color_conv_coef *ct)
 {
 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
@@ -793,27 +798,27 @@ static void dispc_setup_color_conv_coef(void)
 		dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
 }
 
-static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
+static void dispc_ovl_set_ba0(enum omap_plane_id plane, u32 paddr)
 {
 	dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 }
 
-static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
+static void dispc_ovl_set_ba1(enum omap_plane_id plane, u32 paddr)
 {
 	dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 }
 
-static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
+static void dispc_ovl_set_ba0_uv(enum omap_plane_id plane, u32 paddr)
 {
 	dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 }
 
-static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
+static void dispc_ovl_set_ba1_uv(enum omap_plane_id plane, u32 paddr)
 {
 	dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 }
 
-static void dispc_ovl_set_pos(enum omap_plane plane,
+static void dispc_ovl_set_pos(enum omap_plane_id plane,
 		enum omap_overlay_caps caps, int x, int y)
 {
 	u32 val;
@@ -826,7 +831,7 @@ static void dispc_ovl_set_pos(enum omap_plane plane,
 	dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 }
 
-static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
+static void dispc_ovl_set_input_size(enum omap_plane_id plane, int width,
 		int height)
 {
 	u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
@@ -837,7 +842,7 @@ static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 		dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 }
 
-static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
+static void dispc_ovl_set_output_size(enum omap_plane_id plane, int width,
 		int height)
 {
 	u32 val;
@@ -852,7 +857,7 @@ static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 		dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 }
 
-static void dispc_ovl_set_zorder(enum omap_plane plane,
+static void dispc_ovl_set_zorder(enum omap_plane_id plane,
 		enum omap_overlay_caps caps, u8 zorder)
 {
 	if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
@@ -872,7 +877,7 @@ static void dispc_ovl_enable_zorder_planes(void)
 		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 }
 
-static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
+static void dispc_ovl_set_pre_mult_alpha(enum omap_plane_id plane,
 		enum omap_overlay_caps caps, bool enable)
 {
 	if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
@@ -881,7 +886,7 @@ static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 }
 
-static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
+static void dispc_ovl_setup_global_alpha(enum omap_plane_id plane,
 		enum omap_overlay_caps caps, u8 global_alpha)
 {
 	static const unsigned shifts[] = { 0, 8, 16, 24, };
@@ -894,17 +899,17 @@ static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 	REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 }
 
-static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
+static void dispc_ovl_set_pix_inc(enum omap_plane_id plane, s32 inc)
 {
 	dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 }
 
-static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
+static void dispc_ovl_set_row_inc(enum omap_plane_id plane, s32 inc)
 {
 	dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 }
 
-static void dispc_ovl_set_color_mode(enum omap_plane plane,
+static void dispc_ovl_set_color_mode(enum omap_plane_id plane,
 		enum omap_color_mode color_mode)
 {
 	u32 m = 0;
@@ -985,7 +990,7 @@ static void dispc_ovl_set_color_mode(enum omap_plane plane,
 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 }
 
-static void dispc_ovl_configure_burst_type(enum omap_plane plane,
+static void dispc_ovl_configure_burst_type(enum omap_plane_id plane,
 		enum omap_dss_rotation_type rotation_type)
 {
 	if (dss_has_feature(FEAT_BURST_2D) == 0)
@@ -997,7 +1002,8 @@ static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 }
 
-void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
+void dispc_ovl_set_channel_out(enum omap_plane_id plane,
+			       enum omap_channel channel)
 {
 	int shift;
 	u32 val;
@@ -1059,7 +1065,7 @@ void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 }
 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
 
-static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
+static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane)
 {
 	int shift;
 	u32 val;
@@ -1101,12 +1107,12 @@ static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
 
 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
 {
-	enum omap_plane plane = OMAP_DSS_WB;
+	enum omap_plane_id plane = OMAP_DSS_WB;
 
 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
 }
 
-static void dispc_ovl_set_burst_size(enum omap_plane plane,
+static void dispc_ovl_set_burst_size(enum omap_plane_id plane,
 		enum omap_burst_size burst_size)
 {
 	static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
@@ -1128,7 +1134,7 @@ static void dispc_configure_burst_sizes(void)
 		dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
 }
 
-static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
+static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane)
 {
 	unsigned unit = dss_feat_get_burst_size_unit();
 	/* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
@@ -1163,7 +1169,8 @@ static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
 	dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
 }
 
-static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
+static void dispc_ovl_set_vid_color_conv(enum omap_plane_id plane,
+					 bool enable)
 {
 	u32 val;
 
@@ -1174,7 +1181,7 @@ static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
 	dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 }
 
-static void dispc_ovl_enable_replication(enum omap_plane plane,
+static void dispc_ovl_enable_replication(enum omap_plane_id plane,
 		enum omap_overlay_caps caps, bool enable)
 {
 	static const unsigned shifts[] = { 5, 10, 10, 10 };
@@ -1271,7 +1278,7 @@ static void dispc_init_fifos(void)
 	}
 }
 
-static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
+static u32 dispc_ovl_get_fifo_size(enum omap_plane_id plane)
 {
 	int fifo;
 	u32 size = 0;
@@ -1284,7 +1291,8 @@ static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
 	return size;
 }
 
-void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
+void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
+				  u32 high)
 {
 	u8 hi_start, hi_end, lo_start, lo_end;
 	u32 unit;
@@ -1333,7 +1341,7 @@ void dispc_enable_fifomerge(bool enable)
 	REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
 }
 
-void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
+void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
 		u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
 		bool manual_update)
 {
@@ -1380,7 +1388,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
 	}
 }
 
-static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
+static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable)
 {
 	int bit;
 
@@ -1392,7 +1400,7 @@ static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
 }
 
-static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
+static void dispc_ovl_set_mflag_threshold(enum omap_plane_id plane,
 	int low, int high)
 {
 	dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
@@ -1456,7 +1464,7 @@ static void dispc_init_mflag(void)
 	}
 }
 
-static void dispc_ovl_set_fir(enum omap_plane plane,
+static void dispc_ovl_set_fir(enum omap_plane_id plane,
 				int hinc, int vinc,
 				enum omap_color_component color_comp)
 {
@@ -1479,7 +1487,8 @@ static void dispc_ovl_set_fir(enum omap_plane plane,
 	}
 }
 
-static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
+static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu,
+				    int vaccu)
 {
 	u32 val;
 	u8 hor_start, hor_end, vert_start, vert_end;
@@ -1493,7 +1502,8 @@ static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
 	dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
 }
 
-static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
+static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu,
+				    int vaccu)
 {
 	u32 val;
 	u8 hor_start, hor_end, vert_start, vert_end;
@@ -1507,7 +1517,7 @@ static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
 	dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
 }
 
-static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
+static void dispc_ovl_set_vid_accu2_0(enum omap_plane_id plane, int haccu,
 		int vaccu)
 {
 	u32 val;
@@ -1516,7 +1526,7 @@ static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
 	dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
 }
 
-static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
+static void dispc_ovl_set_vid_accu2_1(enum omap_plane_id plane, int haccu,
 		int vaccu)
 {
 	u32 val;
@@ -1525,7 +1535,7 @@ static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
 	dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
 }
 
-static void dispc_ovl_set_scale_param(enum omap_plane plane,
+static void dispc_ovl_set_scale_param(enum omap_plane_id plane,
 		u16 orig_width, u16 orig_height,
 		u16 out_width, u16 out_height,
 		bool five_taps, u8 rotation,
@@ -1541,7 +1551,7 @@ static void dispc_ovl_set_scale_param(enum omap_plane plane,
 	dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
 }
 
-static void dispc_ovl_set_accu_uv(enum omap_plane plane,
+static void dispc_ovl_set_accu_uv(enum omap_plane_id plane,
 		u16 orig_width,	u16 orig_height, u16 out_width, u16 out_height,
 		bool ilace, enum omap_color_mode color_mode, u8 rotation)
 {
@@ -1629,7 +1639,7 @@ static void dispc_ovl_set_accu_uv(enum omap_plane plane,
 	dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
 }
 
-static void dispc_ovl_set_scaling_common(enum omap_plane plane,
+static void dispc_ovl_set_scaling_common(enum omap_plane_id plane,
 		u16 orig_width, u16 orig_height,
 		u16 out_width, u16 out_height,
 		bool ilace, bool five_taps,
@@ -1683,7 +1693,7 @@ static void dispc_ovl_set_scaling_common(enum omap_plane plane,
 	dispc_ovl_set_vid_accu1(plane, 0, accu1);
 }
 
-static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
+static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane,
 		u16 orig_width, u16 orig_height,
 		u16 out_width, u16 out_height,
 		bool ilace, bool five_taps,
@@ -1763,7 +1773,7 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
 }
 
-static void dispc_ovl_set_scaling(enum omap_plane plane,
+static void dispc_ovl_set_scaling(enum omap_plane_id plane,
 		u16 orig_width, u16 orig_height,
 		u16 out_width, u16 out_height,
 		bool ilace, bool five_taps,
@@ -1787,7 +1797,8 @@ static void dispc_ovl_set_scaling(enum omap_plane plane,
 		rotation);
 }
 
-static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
+static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane,
+					 u8 rotation,
 		enum omap_dss_rotation_type rotation_type,
 		bool mirroring, enum omap_color_mode color_mode)
 {
@@ -2619,7 +2630,7 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
 	return 0;
 }
 
-static int dispc_ovl_setup_common(enum omap_plane plane,
+static int dispc_ovl_setup_common(enum omap_plane_id plane,
 		enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
 		u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
 		u16 out_width, u16 out_height, enum omap_color_mode color_mode,
@@ -2817,7 +2828,8 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
 	return 0;
 }
 
-int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
+int dispc_ovl_setup(enum omap_plane_id plane,
+		    const struct omap_overlay_info *oi,
 		bool replication, const struct videomode *vm,
 		bool mem_to_mem)
 {
@@ -2848,7 +2860,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
 {
 	int r;
 	u32 l;
-	enum omap_plane plane = OMAP_DSS_WB;
+	enum omap_plane_id plane = OMAP_DSS_WB;
 	const int pos_x = 0, pos_y = 0;
 	const u8 zorder = 0, global_alpha = 0;
 	const bool replication = false;
@@ -2911,7 +2923,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
 	return r;
 }
 
-int dispc_ovl_enable(enum omap_plane plane, bool enable)
+int dispc_ovl_enable(enum omap_plane_id plane, bool enable)
 {
 	DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
 
@@ -2921,7 +2933,7 @@ int dispc_ovl_enable(enum omap_plane plane, bool enable)
 }
 EXPORT_SYMBOL(dispc_ovl_enable);
 
-bool dispc_ovl_enabled(enum omap_plane plane)
+bool dispc_ovl_enabled(enum omap_plane_id plane)
 {
 	return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
 }
@@ -3389,7 +3401,7 @@ static unsigned long dispc_core_clk_rate(void)
 	return dispc.core_clk_rate;
 }
 
-static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
+static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane)
 {
 	enum omap_channel channel;
 
@@ -3401,7 +3413,7 @@ static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
 	return dispc_mgr_pclk_rate(channel);
 }
 
-static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
+static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane)
 {
 	enum omap_channel channel;
 
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.h b/drivers/gpu/drm/omapdrm/dss/dispc.h
index bc1d812..003adce 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.h
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.h
@@ -353,7 +353,7 @@ static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
 }
 
 /* DISPC overlay register base addresses */
-static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
+static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -373,7 +373,7 @@ static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
 }
 
 /* DISPC overlay register offsets */
-static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -389,7 +389,7 @@ static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -405,7 +405,7 @@ static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -425,7 +425,7 @@ static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -445,7 +445,7 @@ static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_POS_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -460,7 +460,7 @@ static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_SIZE_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -476,7 +476,7 @@ static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_ATTR_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -493,7 +493,7 @@ static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -513,7 +513,7 @@ static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -530,7 +530,7 @@ static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -547,7 +547,7 @@ static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -564,7 +564,7 @@ static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -581,7 +581,7 @@ static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -597,7 +597,7 @@ static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -613,7 +613,7 @@ static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_FIR_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -631,7 +631,7 @@ static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_FIR2_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -651,7 +651,7 @@ static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -670,7 +670,7 @@ static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 }
 
 
-static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -688,7 +688,7 @@ static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -708,7 +708,7 @@ static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -726,7 +726,7 @@ static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -747,7 +747,7 @@ static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
 }
 
 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
+static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane, u16 i)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -766,7 +766,7 @@ static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 }
 
 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
+static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane, u16 i)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -787,7 +787,7 @@ static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
 }
 
 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
+static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane, u16 i)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -806,7 +806,7 @@ static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 }
 
 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
+static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane, u16 i)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -827,7 +827,7 @@ static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
 }
 
 /* coef index i = {0, 1, 2, 3, 4,} */
-static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
+static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane, u16 i)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -845,7 +845,7 @@ static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 }
 
 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
+static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane, u16 i)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -865,7 +865,7 @@ static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 }
 
 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
+static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane, u16 i)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -885,7 +885,7 @@ static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
 	}
 }
 
-static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -902,7 +902,7 @@ static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 	}
 }
 
-static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
+static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane)
 {
 	switch (plane) {
 	case OMAP_DSS_GFX:
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h
index 78f6fc7..9b769dc 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.h
+++ b/drivers/gpu/drm/omapdrm/dss/dss.h
@@ -368,8 +368,9 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 		struct dispc_clock_info *cinfo);
 
 
-void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
-void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
+void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
+				  u32 high);
+void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
 		u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
 		bool manual_update);
 
diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c
index ee5b93c..8ac3cbc 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss_features.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c
@@ -802,18 +802,18 @@ enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel
 	return omap_current_dss_features->supported_outputs[channel];
 }
 
-enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
+enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane)
 {
 	return omap_current_dss_features->supported_color_modes[plane];
 }
 EXPORT_SYMBOL(dss_feat_get_supported_color_modes);
 
-enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
+enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane)
 {
 	return omap_current_dss_features->overlay_caps[plane];
 }
 
-bool dss_feat_color_mode_supported(enum omap_plane plane,
+bool dss_feat_color_mode_supported(enum omap_plane_id plane,
 		enum omap_color_mode color_mode)
 {
 	return omap_current_dss_features->supported_color_modes[plane] &
diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h
index bb4b7f0..603f3ae 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss_features.h
+++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h
@@ -88,8 +88,8 @@ enum dss_range_param {
 /* DSS Feature Functions */
 unsigned long dss_feat_get_param_min(enum dss_range_param param);
 unsigned long dss_feat_get_param_max(enum dss_range_param param);
-enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane);
-bool dss_feat_color_mode_supported(enum omap_plane plane,
+enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane);
+bool dss_feat_color_mode_supported(enum omap_plane_id plane,
 		enum omap_color_mode color_mode);
 
 u32 dss_feat_get_buffer_size_unit(void);	/* in bytes */
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index 5b3b961..9b1a55f 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -76,7 +76,7 @@ enum omap_display_type {
 	OMAP_DISPLAY_TYPE_DVI		= 1 << 6,
 };
 
-enum omap_plane {
+enum omap_plane_id {
 	OMAP_DSS_GFX	= 0,
 	OMAP_DSS_VIDEO1	= 1,
 	OMAP_DSS_VIDEO2	= 2,
@@ -338,7 +338,7 @@ struct omap_overlay {
 
 	/* static fields */
 	const char *name;
-	enum omap_plane id;
+	enum omap_plane_id id;
 	enum omap_color_mode supported_modes;
 	enum omap_overlay_caps caps;
 
@@ -785,7 +785,7 @@ struct omap_dss_device *omap_dss_find_device(void *data,
 
 int dss_feat_get_num_mgrs(void);
 int dss_feat_get_num_ovls(void);
-enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
+enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane);
 
 
 
@@ -872,11 +872,12 @@ void dispc_mgr_set_gamma(enum omap_channel channel,
 			 const struct drm_color_lut *lut,
 			 unsigned int length);
 
-int dispc_ovl_enable(enum omap_plane plane, bool enable);
-bool dispc_ovl_enabled(enum omap_plane plane);
-void dispc_ovl_set_channel_out(enum omap_plane plane,
+int dispc_ovl_enable(enum omap_plane_id plane, bool enable);
+bool dispc_ovl_enabled(enum omap_plane_id plane);
+void dispc_ovl_set_channel_out(enum omap_plane_id plane,
 		enum omap_channel channel);
-int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
+int dispc_ovl_setup(enum omap_plane_id plane,
+		    const struct omap_overlay_info *oi,
 		bool replication, const struct videomode *vm, bool mem_to_mem);
 
 enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v3 3/5] drm/omap: Fix ugliest indentation style breaks from previous patch

[Jyri Sarha]

Fix the most ugly indentation style breaks left by the previous
coccilnelle patch.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/gpu/drm/omapdrm/dss/dispc.c   | 5 ++---
 drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 +-
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 17712a3..c7457ad 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -1797,8 +1797,7 @@ static void dispc_ovl_set_scaling(enum omap_plane_id plane,
 		rotation);
 }
 
-static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane,
-					 u8 rotation,
+static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation,
 		enum omap_dss_rotation_type rotation_type,
 		bool mirroring, enum omap_color_mode color_mode)
 {
@@ -2829,7 +2828,7 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane,
 }
 
 int dispc_ovl_setup(enum omap_plane_id plane,
-		    const struct omap_overlay_info *oi,
+		const struct omap_overlay_info *oi,
 		bool replication, const struct videomode *vm,
 		bool mem_to_mem)
 {
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index 9b1a55f..b1b7b9d 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -877,7 +877,7 @@ void dispc_mgr_set_gamma(enum omap_channel channel,
 void dispc_ovl_set_channel_out(enum omap_plane_id plane,
 		enum omap_channel channel);
 int dispc_ovl_setup(enum omap_plane_id plane,
-		    const struct omap_overlay_info *oi,
+		const struct omap_overlay_info *oi,
 		bool replication, const struct videomode *vm, bool mem_to_mem);
 
 enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v3 4/5] drm/omap: Remove the obsolete #define omap_plane _omap_plane hack

[Jyri Sarha]

Remove the obsolete "#define omap_plane _omap_plane" hack and other
related hacks to get around the enum omap_plane colliding with struct
omap_plane.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/gpu/drm/omapdrm/omap_plane.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c
index 386d90a..1e0c0e7 100644
--- a/drivers/gpu/drm/omapdrm/omap_plane.c
+++ b/drivers/gpu/drm/omapdrm/omap_plane.c
@@ -24,12 +24,6 @@
 #include "omap_dmm_tiler.h"
 #include "omap_drv.h"
 
-/* some hackery because omapdss has an 'enum omap_plane' (which would be
- * better named omap_plane_id).. and compiler seems unhappy about having
- * both a 'struct omap_plane' and 'enum omap_plane'
- */
-#define omap_plane _omap_plane
-
 /*
  * plane funcs
  */
@@ -38,7 +32,7 @@
 
 struct omap_plane {
 	struct drm_plane base;
-	int id;  /* TODO rename omap_plane -> omap_plane_id in omapdss so I can use the enum */
+	enum omap_plane_id id;
 	const char *name;
 
 	uint32_t nformats;
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v3 5/5] drm/omap: Major omap_modeset_init() cleanup

[Jyri Sarha]

Cleanup overly complex omap_modeset_init(). The function is trying to
support many unusual configuration, that have never been tested and
are not supported by other parts of the dirver.

After cleanup the init function creates exactly one connector,
encoder, crtc, and primary plane per each connected dss-device. Each
connector->encoder->crtc chain is expected to be separate and each
crtc is connect to a single dss-channel. If the configuration does not
match the expectations or exceeds the available resources, the
configuration is rejected.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/gpu/drm/omapdrm/omap_crtc.c  |  20 +++-
 drivers/gpu/drm/omapdrm/omap_drv.c   | 177 ++++++++++-------------------------
 drivers/gpu/drm/omapdrm/omap_drv.h   |   4 +-
 drivers/gpu/drm/omapdrm/omap_plane.c |  24 ++++-
 4 files changed, 86 insertions(+), 139 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index 2fe735c..702df04 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -521,6 +521,8 @@ static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
 
 void omap_crtc_pre_init(void)
 {
+	memset(omap_crtcs, 0, sizeof(omap_crtcs));
+
 	dss_install_mgr_ops(&mgr_ops);
 }
 
@@ -531,17 +533,27 @@ void omap_crtc_pre_uninit(void)
 
 /* initialize crtc */
 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
-		struct drm_plane *plane, enum omap_channel channel, int id)
+		struct drm_plane *plane, struct omap_dss_device *dssdev)
 {
 	struct drm_crtc *crtc = NULL;
 	struct omap_crtc *omap_crtc;
+	enum omap_channel channel;
+	struct omap_dss_device *out;
 	int ret;
 
+	out = omapdss_find_output_from_display(dssdev);
+	channel = out->dispc_channel;
+	omap_dss_put_device(out);
+
 	DBG("%s", channel_names[channel]);
 
+	/* Multiple displays on same channel is not allowed */
+	if (WARN_ON(omap_crtcs[channel] != NULL))
+		return ERR_PTR(-EINVAL);
+
 	omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
 	if (!omap_crtc)
-		return NULL;
+		return ERR_PTR(-ENOMEM);
 
 	crtc = &omap_crtc->base;
 
@@ -553,8 +565,10 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev,
 	ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
 					&omap_crtc_funcs, NULL);
 	if (ret < 0) {
+		dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
+			__func__, dssdev->name);
 		kfree(omap_crtc);
-		return NULL;
+		return ERR_PTR(ret);
 	}
 
 	drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index 17c40aa..12fbb12 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -219,20 +219,6 @@ static int get_connector_type(struct omap_dss_device *dssdev)
 	}
 }
 
-static bool channel_used(struct drm_device *dev, enum omap_channel channel)
-{
-	struct omap_drm_private *priv = dev->dev_private;
-	int i;
-
-	for (i = 0; i < priv->num_crtcs; i++) {
-		struct drm_crtc *crtc = priv->crtcs[i];
-
-		if (omap_crtc_channel(crtc) == channel)
-			return true;
-	}
-
-	return false;
-}
 static void omap_disconnect_dssdevs(void)
 {
 	struct omap_dss_device *dssdev = NULL;
@@ -275,31 +261,6 @@ static int omap_connect_dssdevs(void)
 	return r;
 }
 
-static int omap_modeset_create_crtc(struct drm_device *dev, int id,
-				    enum omap_channel channel,
-				    u32 possible_crtcs)
-{
-	struct omap_drm_private *priv = dev->dev_private;
-	struct drm_plane *plane;
-	struct drm_crtc *crtc;
-
-	plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_PRIMARY,
-		possible_crtcs);
-	if (IS_ERR(plane))
-		return PTR_ERR(plane);
-
-	crtc = omap_crtc_init(dev, plane, channel, id);
-
-	BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs));
-	priv->crtcs[id] = crtc;
-	priv->num_crtcs++;
-
-	priv->planes[id] = plane;
-	priv->num_planes++;
-
-	return 0;
-}
-
 static int omap_modeset_init_properties(struct drm_device *dev)
 {
 	struct omap_drm_private *priv = dev->dev_private;
@@ -317,10 +278,9 @@ static int omap_modeset_init(struct drm_device *dev)
 	struct omap_dss_device *dssdev = NULL;
 	int num_ovls = dss_feat_get_num_ovls();
 	int num_mgrs = dss_feat_get_num_mgrs();
-	int num_crtcs = 0;
-	int i, id = 0;
+	int num_crtcs, crtc_idx, plane_idx;
 	int ret;
-	u32 possible_crtcs;
+	u32 plane_crtc_mask;
 
 	drm_mode_config_init(dev);
 
@@ -329,134 +289,91 @@ static int omap_modeset_init(struct drm_device *dev)
 		return ret;
 
 	/*
-	 * Let's create one CRTC for each connected DSS device if we
-	 * have display managers and overlays (for primary planes) for
-	 * them.
+	 * This function creates exactly one connector, encoder, crtc,
+	 * and primary plane per each connected dss-device. Each
+	 * connector->encoder->crtc chain is expected to be separate
+	 * and each crtc is connect to a single dss-channel. If the
+	 * configuration does not match the expectations or exceeds
+	 * the available resources, the configuration is rejected.
 	 */
+	num_crtcs = 0;
 	for_each_dss_dev(dssdev)
 		if (omapdss_device_is_connected(dssdev))
 			num_crtcs++;
 
-	num_crtcs = min3(num_crtcs, num_mgrs, num_ovls);
-	possible_crtcs = (1 << num_crtcs) - 1;
+	if (num_crtcs > num_mgrs || num_crtcs > num_ovls ||
+	    num_crtcs > ARRAY_SIZE(priv->crtcs) ||
+	    num_crtcs > ARRAY_SIZE(priv->planes) ||
+	    num_crtcs > ARRAY_SIZE(priv->encoders) ||
+	    num_crtcs > ARRAY_SIZE(priv->connectors)) {
+		dev_err(dev->dev, "%s(): Too many connected displays\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	/* All planes can be put to any CRTC */
+	plane_crtc_mask = (1 << num_crtcs) - 1;
 
 	dssdev = NULL;
 
+	crtc_idx = 0;
+	plane_idx = 0;
 	for_each_dss_dev(dssdev) {
 		struct drm_connector *connector;
 		struct drm_encoder *encoder;
-		enum omap_channel channel;
-		struct omap_dss_device *out;
+		struct drm_plane *plane;
+		struct drm_crtc *crtc;
 
 		if (!omapdss_device_is_connected(dssdev))
 			continue;
 
 		encoder = omap_encoder_init(dev, dssdev);
-
-		if (!encoder) {
-			dev_err(dev->dev, "could not create encoder: %s\n",
-					dssdev->name);
+		if (!encoder)
 			return -ENOMEM;
-		}
 
 		connector = omap_connector_init(dev,
 				get_connector_type(dssdev), dssdev, encoder);
-
-		if (!connector) {
-			dev_err(dev->dev, "could not create connector: %s\n",
-					dssdev->name);
+		if (!connector)
 			return -ENOMEM;
-		}
 
-		BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders));
-		BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors));
+		plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_PRIMARY,
+					plane_crtc_mask);
+		if (IS_ERR(plane))
+			return PTR_ERR(plane);
 
-		priv->encoders[priv->num_encoders++] = encoder;
-		priv->connectors[priv->num_connectors++] = connector;
+		crtc = omap_crtc_init(dev, plane, dssdev);
+		if (IS_ERR(crtc))
+			return PTR_ERR(crtc);
 
 		drm_mode_connector_attach_encoder(connector, encoder);
+		encoder->possible_crtcs = (1 << crtc_idx);
 
-		/*
-		 * if we have reached the limit of the crtcs we can
-		 * create, let's not try to create a crtc for this
-		 * panel/encoder and onwards.
-		 */
-		if (id == num_crtcs)
-			continue;
+		priv->crtcs[priv->num_crtcs++] = crtc;
+		priv->planes[priv->num_planes++] = plane;
+		priv->encoders[priv->num_encoders++] = encoder;
+		priv->connectors[priv->num_connectors++] = connector;
 
-		/*
-		 * get the recommended DISPC channel for this encoder. For now,
-		 * we only try to get create a crtc out of the recommended, the
-		 * other possible channels to which the encoder can connect are
-		 * not considered.
-		 */
-
-		out = omapdss_find_output_from_display(dssdev);
-		channel = out->dispc_channel;
-		omap_dss_put_device(out);
-
-		/*
-		 * if this channel hasn't already been taken by a previously
-		 * allocated crtc, we create a new crtc for it
-		 */
-		if (!channel_used(dev, channel)) {
-			ret = omap_modeset_create_crtc(dev, id, channel,
-				possible_crtcs);
-			if (ret < 0) {
-				dev_err(dev->dev,
-					"could not create CRTC (channel %u)\n",
-					channel);
-				return ret;
-			}
-
-			id++;
-		}
+		plane_idx++;
+		crtc_idx++;
 	}
 
 	/*
 	 * Create normal planes for the remaining overlays:
 	 */
-	for (; id < num_ovls; id++) {
+	for (; plane_idx < num_ovls; plane_idx++) {
 		struct drm_plane *plane;
 
-		plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_OVERLAY,
-			possible_crtcs);
+		if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
+			return -EINVAL;
+
+		plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_OVERLAY,
+			plane_crtc_mask);
 		if (IS_ERR(plane))
 			return PTR_ERR(plane);
 
-		BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes));
 		priv->planes[priv->num_planes++] = plane;
 	}
 
-	/*
-	 * populate the the possible_crtcs field for all the encoders
-	 * we created.
-	 */
-	for (i = 0; i < priv->num_encoders; i++) {
-		struct drm_encoder *encoder = priv->encoders[i];
-		struct omap_dss_device *dssdev =
-					omap_encoder_get_dssdev(encoder);
-		struct omap_dss_device *output;
-
-		output = omapdss_find_output_from_display(dssdev);
-
-		/* figure out which crtc's we can connect the encoder to: */
-		encoder->possible_crtcs = 0;
-		for (id = 0; id < priv->num_crtcs; id++) {
-			struct drm_crtc *crtc = priv->crtcs[id];
-			enum omap_channel crtc_channel;
-
-			crtc_channel = omap_crtc_channel(crtc);
-
-			if (output->dispc_channel == crtc_channel) {
-				encoder->possible_crtcs |= (1 << id);
-				break;
-			}
-		}
-
-		omap_dss_put_device(output);
-	}
-
 	DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
 		priv->num_planes, priv->num_crtcs, priv->num_encoders,
 		priv->num_connectors);
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h
index 9098ea1..9f636f4 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -135,13 +135,13 @@ static inline void omap_fbdev_free(struct drm_device *dev)
 void omap_crtc_pre_init(void);
 void omap_crtc_pre_uninit(void);
 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
-		struct drm_plane *plane, enum omap_channel channel, int id);
+		struct drm_plane *plane, struct omap_dss_device *dssdev);
 int omap_crtc_wait_pending(struct drm_crtc *crtc);
 void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus);
 void omap_crtc_vblank_irq(struct drm_crtc *crtc);
 
 struct drm_plane *omap_plane_init(struct drm_device *dev,
-		int id, enum drm_plane_type type,
+		int idx, enum drm_plane_type type,
 		u32 possible_crtcs);
 void omap_plane_install_properties(struct drm_plane *plane,
 		struct drm_mode_object *obj);
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c
index 1e0c0e7..757c037 100644
--- a/drivers/gpu/drm/omapdrm/omap_plane.c
+++ b/drivers/gpu/drm/omapdrm/omap_plane.c
@@ -322,23 +322,36 @@ static int omap_plane_atomic_get_property(struct drm_plane *plane,
 	.atomic_get_property = omap_plane_atomic_get_property,
 };
 
-static const char *plane_names[] = {
+static const char *plane_id_to_name[] = {
 	[OMAP_DSS_GFX] = "gfx",
 	[OMAP_DSS_VIDEO1] = "vid1",
 	[OMAP_DSS_VIDEO2] = "vid2",
 	[OMAP_DSS_VIDEO3] = "vid3",
 };
 
+static const enum omap_plane_id plane_idx_to_id[] = {
+	OMAP_DSS_GFX,
+	OMAP_DSS_VIDEO1,
+	OMAP_DSS_VIDEO2,
+	OMAP_DSS_VIDEO3,
+};
+
 /* initialize plane */
 struct drm_plane *omap_plane_init(struct drm_device *dev,
-		int id, enum drm_plane_type type,
+		int idx, enum drm_plane_type type,
 		u32 possible_crtcs)
 {
 	struct drm_plane *plane;
 	struct omap_plane *omap_plane;
+	enum omap_plane_id id;
 	int ret;
 
-	DBG("%s: type=%d", plane_names[id], type);
+	if (WARN_ON(idx >= ARRAY_SIZE(plane_idx_to_id)))
+		return ERR_PTR(-EINVAL);
+
+	id = plane_idx_to_id[idx];
+
+	DBG("%s: type=%d", plane_id_to_name[id], type);
 
 	omap_plane = kzalloc(sizeof(*omap_plane), GFP_KERNEL);
 	if (!omap_plane)
@@ -348,7 +361,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev,
 			omap_plane->formats, ARRAY_SIZE(omap_plane->formats),
 			dss_feat_get_supported_color_modes(id));
 	omap_plane->id = id;
-	omap_plane->name = plane_names[id];
+	omap_plane->name = plane_id_to_name[id];
 
 	plane = &omap_plane->base;
 
@@ -365,6 +378,9 @@ struct drm_plane *omap_plane_init(struct drm_device *dev,
 	return plane;
 
 error:
+	dev_err(dev->dev, "%s(): could not create plane: %s\n",
+		__func__, plane_id_to_name[id]);
+
 	kfree(omap_plane);
 	return NULL;
 }
-- 
1.9.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel