From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37C24C61DA4 for ; Wed, 22 Feb 2023 17:33:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B3F010EA73; Wed, 22 Feb 2023 17:33:57 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 614CF10E3D7; Wed, 22 Feb 2023 17:33:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677087234; x=1708623234; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=dBfK1f9SoIdQd//p3pK+J5jmUGdNq+Hb8SM5LrvByCw=; b=P8lCFfGDPzXNw6pFFWArYMCRDAL/xrwKgHh6jn1SfoC3F8On0TSzfeAD +R4o+pdlmU8KOt9mLNg22EQseMUhkD5M68d83kiBdBUmiYUlzwzr0/H/1 nlJLJx0eng5WdqwqH55lPKhqJ5UVfB3bhREVHVrVnKHWF1RXwRMavnJ4m A9WGb/4lmNGfSzA/yEIIp6Sn1HqQdEVI8Ez2IQwfQMWhumB+5v8pmxdgl tYdoAOBU0JL+3okRVBJxXgIkBePMzIhFoImnipiHP5U7853w0BwMiomRa qyk7aI81WAVNeJmLMHiNYNcYhivo5AY3aOAymbqwQXil6Djc3hLliEc6F Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10629"; a="321129867" X-IronPort-AV: E=Sophos;i="5.97,319,1669104000"; d="scan'208";a="321129867" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2023 09:33:47 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10629"; a="704541133" X-IronPort-AV: E=Sophos;i="5.97,319,1669104000"; d="scan'208";a="704541133" Received: from hhammad-mobl1.ger.corp.intel.com (HELO [10.213.231.87]) ([10.213.231.87]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2023 09:33:43 -0800 Message-ID: Date: Wed, 22 Feb 2023 17:33:41 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v4 01/14] dma-buf/dma-fence: Add deadline awareness Content-Language: en-US To: Rob Clark References: <20230218211608.1630586-1-robdclark@gmail.com> <20230218211608.1630586-2-robdclark@gmail.com> <21f36640-3229-0b46-31a2-a47efc5be934@amd.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Pekka Paalanen , Tvrtko Ursulin , Gustavo Padovan , =?UTF-8?Q?Michel_D=c3=a4nzer?= , open list , dri-devel@lists.freedesktop.org, Sumit Semwal , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Rodrigo Vivi , Alex Deucher , freedreno@lists.freedesktop.org, =?UTF-8?Q?Christian_K=c3=b6nig?= , "open list:SYNC FILE FRAMEWORK" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 22/02/2023 17:16, Rob Clark wrote: > On Wed, Feb 22, 2023 at 9:05 AM Tvrtko Ursulin > wrote: >> >> >> On 22/02/2023 15:28, Christian König wrote: >>> Am 22.02.23 um 11:23 schrieb Tvrtko Ursulin: >>>> >>>> On 18/02/2023 21:15, Rob Clark wrote: >>>>> From: Rob Clark >>>>> >>>>> Add a way to hint to the fence signaler of an upcoming deadline, such as >>>>> vblank, which the fence waiter would prefer not to miss. This is to aid >>>>> the fence signaler in making power management decisions, like boosting >>>>> frequency as the deadline approaches and awareness of missing deadlines >>>>> so that can be factored in to the frequency scaling. >>>>> >>>>> v2: Drop dma_fence::deadline and related logic to filter duplicate >>>>> deadlines, to avoid increasing dma_fence size. The fence-context >>>>> implementation will need similar logic to track deadlines of all >>>>> the fences on the same timeline. [ckoenig] >>>>> v3: Clarify locking wrt. set_deadline callback >>>>> >>>>> Signed-off-by: Rob Clark >>>>> Reviewed-by: Christian König >>>>> --- >>>>> drivers/dma-buf/dma-fence.c | 20 ++++++++++++++++++++ >>>>> include/linux/dma-fence.h | 20 ++++++++++++++++++++ >>>>> 2 files changed, 40 insertions(+) >>>>> >>>>> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c >>>>> index 0de0482cd36e..763b32627684 100644 >>>>> --- a/drivers/dma-buf/dma-fence.c >>>>> +++ b/drivers/dma-buf/dma-fence.c >>>>> @@ -912,6 +912,26 @@ dma_fence_wait_any_timeout(struct dma_fence >>>>> **fences, uint32_t count, >>>>> } >>>>> EXPORT_SYMBOL(dma_fence_wait_any_timeout); >>>>> + >>>>> +/** >>>>> + * dma_fence_set_deadline - set desired fence-wait deadline >>>>> + * @fence: the fence that is to be waited on >>>>> + * @deadline: the time by which the waiter hopes for the fence to be >>>>> + * signaled >>>>> + * >>>>> + * Inform the fence signaler of an upcoming deadline, such as >>>>> vblank, by >>>>> + * which point the waiter would prefer the fence to be signaled by. >>>>> This >>>>> + * is intended to give feedback to the fence signaler to aid in power >>>>> + * management decisions, such as boosting GPU frequency if a periodic >>>>> + * vblank deadline is approaching. >>>>> + */ >>>>> +void dma_fence_set_deadline(struct dma_fence *fence, ktime_t deadline) >>>>> +{ >>>>> + if (fence->ops->set_deadline && !dma_fence_is_signaled(fence)) >>>>> + fence->ops->set_deadline(fence, deadline); >>>>> +} >>>>> +EXPORT_SYMBOL(dma_fence_set_deadline); >>>>> + >>>>> /** >>>>> * dma_fence_describe - Dump fence describtion into seq_file >>>>> * @fence: the 6fence to describe >>>>> diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h >>>>> index 775cdc0b4f24..d77f6591c453 100644 >>>>> --- a/include/linux/dma-fence.h >>>>> +++ b/include/linux/dma-fence.h >>>>> @@ -99,6 +99,7 @@ enum dma_fence_flag_bits { >>>>> DMA_FENCE_FLAG_SIGNALED_BIT, >>>>> DMA_FENCE_FLAG_TIMESTAMP_BIT, >>>>> DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >>>>> + DMA_FENCE_FLAG_HAS_DEADLINE_BIT, >>>> >>>> Would this bit be better left out from core implementation, given how >>>> the approach is the component which implements dma-fence has to track >>>> the actual deadline and all? >>>> >>>> Also taking a step back - are we all okay with starting to expand the >>>> relatively simple core synchronisation primitive with side channel >>>> data like this? What would be the criteria for what side channel data >>>> would be acceptable? Taking note the thing lives outside drivers/gpu/. >>> >>> I had similar concerns and it took me a moment as well to understand the >>> background why this is necessary. I essentially don't see much other >>> approach we could do. >>> >>> Yes, this is GPU/CRTC specific, but we somehow need a common interface >>> for communicating it between drivers and that's the dma_fence object as >>> far as I can see. >> >> Yeah I also don't see any other easy options. Just wanted to raise this >> as something which probably needs some wider acks. >> >> Also what about the "low level" part of my question about the reason, or >> benefits, of defining the deadline bit in the common layer? > > We could leave DMA_FENCE_FLAG_HAS_DEADLINE_BIT out, but OTOH managing > a bitmask that is partially defined in core enum and partially in > backend-driver has it's own drawbacks, and it isn't like we are > running out of bits.. :shrug: There is DMA_FENCE_FLAG_USER_BITS onwards which implementations could use to store their stuff? And if we skip forward to "drm/scheduler: Add fence deadline support" that's the only place bit is used, right? Would it simply work to look at drm_sched_fence->deadline == 0 as bit not set? Or you see a need to interoperate with other fence implementations via that bit somehow? Regards, Tvrtko