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Wed, 28 Jan 2026 08:02:20 +0000 Message-ID: Date: Wed, 28 Jan 2026 09:02:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 5/9] drm/bridge: add a driver for T-Head TH1520 HDMI controller To: Icenowy Zheng , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei Cc: Philipp Zabel , Dmitry Baryshkov , Michal Wilczynski , Luca Ceresoli , Han Gao , Yao Zi , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Han Gao References: <20260123092830.4046009-1-zhengxingda@iscas.ac.cn> <20260123092830.4046009-6-zhengxingda@iscas.ac.cn> Content-Language: en-US From: Thomas Zimmermann Autocrypt: addr=tzimmermann@suse.de; keydata= xsBNBFs50uABCADEHPidWt974CaxBVbrIBwqcq/WURinJ3+2WlIrKWspiP83vfZKaXhFYsdg XH47fDVbPPj+d6tQrw5lPQCyqjwrCPYnq3WlIBnGPJ4/jreTL6V+qfKRDlGLWFjZcsrPJGE0 BeB5BbqP5erN1qylK9i3gPoQjXGhpBpQYwRrEyQyjuvk+Ev0K1Jc5tVDeJAuau3TGNgah4Yc hdHm3bkPjz9EErV85RwvImQ1dptvx6s7xzwXTgGAsaYZsL8WCwDaTuqFa1d1jjlaxg6+tZsB 9GluwvIhSezPgnEmimZDkGnZRRSFiGP8yjqTjjWuf0bSj5rUnTGiyLyRZRNGcXmu6hjlABEB AAHNJ1Rob21hcyBaaW1tZXJtYW5uIDx0emltbWVybWFubkBzdXNlLmRlPsLAjgQTAQgAOAIb AwULCQgHAgYVCgkICwIEFgIDAQIeAQIXgBYhBHIX+6yM6c9jRKFo5WgNwR1TC3ojBQJftODH AAoJEGgNwR1TC3ojx1wH/0hKGWugiqDgLNXLRD/4TfHBEKmxIrmfu9Z5t7vwUKfwhFL6hqvo lXPJJKQpQ2z8+X2vZm/slsLn7J1yjrOsoJhKABDi+3QWWSGkaGwRJAdPVVyJMfJRNNNIKwVb U6B1BkX2XDKDGffF4TxlOpSQzdtNI/9gleOoUA8+jy8knnDYzjBNOZqLG2FuTdicBXblz0Mf vg41gd9kCwYXDnD91rJU8tzylXv03E75NCaTxTM+FBXPmsAVYQ4GYhhgFt8S2UWMoaaABLDe 7l5FdnLdDEcbmd8uLU2CaG4W2cLrUaI4jz2XbkcPQkqTQ3EB67hYkjiEE6Zy3ggOitiQGcqp j//OwE0EWznS4AEIAMYmP4M/V+T5RY5at/g7rUdNsLhWv1APYrh9RQefODYHrNRHUE9eosYb T6XMryR9hT8XlGOYRwKWwiQBoWSDiTMo/Xi29jUnn4BXfI2px2DTXwc22LKtLAgTRjP+qbU6 3Y0xnQN29UGDbYgyyK51DW3H0If2a3JNsheAAK+Xc9baj0LGIc8T9uiEWHBnCH+RdhgATnWW GKdDegUR5BkDfDg5O/FISymJBHx2Dyoklv5g4BzkgqTqwmaYzsl8UxZKvbaxq0zbehDda8lv hFXodNFMAgTLJlLuDYOGLK2AwbrS3Sp0AEbkpdJBb44qVlGm5bApZouHeJ/+n+7r12+lqdsA EQEAAcLAdgQYAQgAIAIbDBYhBHIX+6yM6c9jRKFo5WgNwR1TC3ojBQJftOH6AAoJEGgNwR1T C3ojVSkIALpAPkIJPQoURPb1VWjh34l0HlglmYHvZszJWTXYwavHR8+k6Baa6H7ufXNQtThR yIxJrQLW6rV5lm7TjhffEhxVCn37+cg0zZ3j7zIsSS0rx/aMwi6VhFJA5hfn3T0TtrijKP4A SAQO9xD1Zk9/61JWk8OysuIh7MXkl0fxbRKWE93XeQBhIJHQfnc+YBLprdnxR446Sh8Wn/2D Ya8cavuWf2zrB6cZurs048xe0UbSW5AOSo4V9M0jzYI4nZqTmPxYyXbm30Kvmz0rYVRaitYJ 4kyYYMhuULvrJDMjZRvaNe52tkKAvMevcGdt38H4KSVXAylqyQOW5zvPc4/sq9c= In-Reply-To: <20260123092830.4046009-6-zhengxingda@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-1.000]; R_DKIM_ALLOW(-0.20)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; FREEMAIL_TO(0.00)[iscas.ac.cn,intel.com,linaro.org,kernel.org,ideasonboard.com,kwiboo.se,gmail.com,linux.intel.com,ffwll.ch,redhat.com]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; ARC_NA(0.00)[]; RCPT_COUNT_TWELVE(0.00)[29]; FUZZY_RATELIMITED(0.00)[rspamd.com]; MIME_TRACE(0.00)[0:+]; SPAMHAUS_XBL(0.00)[2a07:de40:b281:104:10:150:64:97:from]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; FREEMAIL_CC(0.00)[pengutronix.de,kernel.org,samsung.com,bootlin.com,gmail.com,disroot.org,vger.kernel.org,lists.freedesktop.org,lists.infradead.org,icenowy.me,iscas.ac.cn]; RCVD_TLS_ALL(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; DNSWL_BLOCKED(0.00)[2a07:de40:b281:106:10:150:64:167:received]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; TAGGED_RCPT(0.00)[dt]; DKIM_TRACE(0.00)[suse.de:+]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; R_RATELIMIT(0.00)[to_ip_from(RLhco1tq9et14njsu3qecxcejq)]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:rdns, imap1.dmz-prg2.suse.org:helo, suse.com:url, iscas.ac.cn:email, samsung.com:email, icenowy.me:email, suse.de:dkim, suse.de:mid, suse.de:email] X-Rspamd-Action: no action X-Rspamd-Queue-Id: 39DC133A89 X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Am 23.01.26 um 10:28 schrieb Icenowy Zheng: > From: Icenowy Zheng > > T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired > with DesignWare HDMI TX PHY Gen2) that takes the "DP" output from the > display controller. > > Add a driver for this controller utilizing the common DesignWare HDMI > code in the kernel. > > Signed-off-by: Icenowy Zheng > Signed-off-by: Icenowy Zheng > Tested-by: Han Gao > Tested-by: Michal Wilczynski Acked-by: Thomas Zimmermann > --- > No changes since v3. > > Changes in v2: > - Created a new function to set PHY parameters and refactored the > control flow of the configure_phy callback. > > MAINTAINERS | 1 + > drivers/gpu/drm/bridge/Kconfig | 10 ++ > drivers/gpu/drm/bridge/Makefile | 1 + > drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 173 ++++++++++++++++++++++++ > 4 files changed, 185 insertions(+) > create mode 100644 drivers/gpu/drm/bridge/th1520-dw-hdmi.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 5b11839cba9de..fc04fc007a054 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -22556,6 +22556,7 @@ F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml > F: arch/riscv/boot/dts/thead/ > F: drivers/clk/thead/clk-th1520-ap.c > F: drivers/firmware/thead,th1520-aon.c > +F: drivers/gpu/drm/bridge/th1520-dw-hdmi.c > F: drivers/mailbox/mailbox-th1520.c > F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c > F: drivers/pinctrl/pinctrl-th1520.c > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > index a250afd8d6622..8e19f5fb9ad7c 100644 > --- a/drivers/gpu/drm/bridge/Kconfig > +++ b/drivers/gpu/drm/bridge/Kconfig > @@ -335,6 +335,16 @@ config DRM_THINE_THC63LVD1024 > help > Thine THC63LVD1024 LVDS/parallel converter driver. > > +config DRM_THEAD_TH1520_DW_HDMI > + tristate "T-Head TH1520 DesignWare HDMI bridge" > + depends on OF > + depends on COMMON_CLK > + depends on ARCH_THEAD || COMPILE_TEST > + select DRM_DW_HDMI > + help > + Choose this to enable support for the internal HDMI bridge found > + on the T-Head TH1520 SoC. > + > config DRM_TOSHIBA_TC358762 > tristate "TC358762 DSI/DPI bridge" > depends on OF > diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile > index c7dc03182e592..085b5db45d6fd 100644 > --- a/drivers/gpu/drm/bridge/Makefile > +++ b/drivers/gpu/drm/bridge/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o > obj-$(CONFIG_DRM_SII9234) += sii9234.o > obj-$(CONFIG_DRM_SIMPLE_BRIDGE) += simple-bridge.o > obj-$(CONFIG_DRM_SOLOMON_SSD2825) += ssd2825.o > +obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) += th1520-dw-hdmi.o > obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o > obj-$(CONFIG_DRM_TOSHIBA_TC358762) += tc358762.o > obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o > diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c > new file mode 100644 > index 0000000000000..389eead5f1c45 > --- /dev/null > +++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c > @@ -0,0 +1,173 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2025 Icenowy Zheng > + * > + * Based on rcar_dw_hdmi.c, which is: > + * Copyright (C) 2016 Renesas Electronics Corporation > + * Based on imx8mp-hdmi-tx.c, which is: > + * Copyright (C) 2022 Pengutronix, Lucas Stach > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +#define TH1520_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */ > +#define TH1520_HDMI_PHY_CKSYMTXCTRL 0x09 /* Clock Symbol and Transmitter Control Register */ > +#define TH1520_HDMI_PHY_VLEVCTRL 0x0e /* Voltage Level Control Register */ > +#define TH1520_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */ > +#define TH1520_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */ > +#define TH1520_HDMI_PHY_TXTERM 0x19 /* Transmission Termination Register */ > + > +struct th1520_hdmi_phy_params { > + unsigned long mpixelclock; > + u16 opmode_pllcfg; > + u16 pllcurrgmpctrl; > + u16 plldivctrl; > + u16 cksymtxctrl; > + u16 vlevctrl; > + u16 txterm; > +}; > + > +static const struct th1520_hdmi_phy_params th1520_hdmi_phy_params[] = { > + { 35500000, 0x0003, 0x0283, 0x0628, 0x8088, 0x01a0, 0x0007 }, > + { 44900000, 0x0003, 0x0285, 0x0228, 0x8088, 0x01a0, 0x0007 }, > + { 71000000, 0x0002, 0x1183, 0x0614, 0x8088, 0x01a0, 0x0007 }, > + { 90000000, 0x0002, 0x1142, 0x0214, 0x8088, 0x01a0, 0x0007 }, > + { 121750000, 0x0001, 0x20c0, 0x060a, 0x8088, 0x01a0, 0x0007 }, > + { 165000000, 0x0001, 0x2080, 0x020a, 0x8088, 0x01a0, 0x0007 }, > + { 198000000, 0x0000, 0x3040, 0x0605, 0x83c8, 0x0120, 0x0004 }, > + { 297000000, 0x0000, 0x3041, 0x0205, 0x81dc, 0x0200, 0x0005 }, > + { 371250000, 0x0640, 0x3041, 0x0205, 0x80f6, 0x0140, 0x0000 }, > + { 495000000, 0x0640, 0x3080, 0x0005, 0x80f6, 0x0140, 0x0000 }, > + { 594000000, 0x0640, 0x3080, 0x0005, 0x80fa, 0x01e0, 0x0004 }, > +}; > + > +struct th1520_hdmi { > + struct dw_hdmi_plat_data plat_data; > + struct dw_hdmi *dw_hdmi; > + struct clk *pixclk; > + struct reset_control *mainrst, *prst; > +}; > + > +static enum drm_mode_status > +th1520_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, > + const struct drm_display_info *info, > + const struct drm_display_mode *mode) > +{ > + /* > + * The maximum supported clock frequency is 594 MHz, as shown in the PHY > + * parameters table. > + */ > + if (mode->clock > 594000) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > + > +static void th1520_hdmi_phy_set_params(struct dw_hdmi *hdmi, > + const struct th1520_hdmi_phy_params *params) > +{ > + dw_hdmi_phy_i2c_write(hdmi, params->opmode_pllcfg, > + TH1520_HDMI_PHY_OPMODE_PLLCFG); > + dw_hdmi_phy_i2c_write(hdmi, params->pllcurrgmpctrl, > + TH1520_HDMI_PHY_PLLCURRGMPCTRL); > + dw_hdmi_phy_i2c_write(hdmi, params->plldivctrl, > + TH1520_HDMI_PHY_PLLDIVCTRL); > + dw_hdmi_phy_i2c_write(hdmi, params->vlevctrl, > + TH1520_HDMI_PHY_VLEVCTRL); > + dw_hdmi_phy_i2c_write(hdmi, params->cksymtxctrl, > + TH1520_HDMI_PHY_CKSYMTXCTRL); > + dw_hdmi_phy_i2c_write(hdmi, params->txterm, > + TH1520_HDMI_PHY_TXTERM); > +} > + > +static int th1520_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, > + unsigned long mpixelclock) > +{ > + unsigned int i; > + > + for (i = 0; i < ARRAY_SIZE(th1520_hdmi_phy_params); i++) { > + if (mpixelclock <= th1520_hdmi_phy_params[i].mpixelclock) { > + th1520_hdmi_phy_set_params(hdmi, > + &th1520_hdmi_phy_params[i]); > + return 0; > + } > + } > + > + return -EINVAL; > +} > + > +static int th1520_dw_hdmi_probe(struct platform_device *pdev) > +{ > + struct th1520_hdmi *hdmi; > + struct dw_hdmi_plat_data *plat_data; > + struct device *dev = &pdev->dev; > + > + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); > + if (!hdmi) > + return -ENOMEM; > + > + plat_data = &hdmi->plat_data; > + > + hdmi->pixclk = devm_clk_get_enabled(dev, "pix"); > + if (IS_ERR(hdmi->pixclk)) > + return dev_err_probe(dev, PTR_ERR(hdmi->pixclk), > + "Unable to get pixel clock\n"); > + > + hdmi->mainrst = devm_reset_control_get_exclusive_deasserted(dev, "main"); > + if (IS_ERR(hdmi->mainrst)) > + return dev_err_probe(dev, PTR_ERR(hdmi->mainrst), > + "Unable to get main reset\n"); > + > + hdmi->prst = devm_reset_control_get_exclusive_deasserted(dev, "apb"); > + if (IS_ERR(hdmi->prst)) > + return dev_err_probe(dev, PTR_ERR(hdmi->prst), > + "Unable to get apb reset\n"); > + > + plat_data->output_port = 1; > + plat_data->mode_valid = th1520_hdmi_mode_valid; > + plat_data->configure_phy = th1520_hdmi_phy_configure; > + plat_data->priv_data = hdmi; > + > + hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); > + if (IS_ERR(hdmi)) > + return PTR_ERR(hdmi); > + > + platform_set_drvdata(pdev, hdmi); > + > + return 0; > +} > + > +static void th1520_dw_hdmi_remove(struct platform_device *pdev) > +{ > + struct dw_hdmi *hdmi = platform_get_drvdata(pdev); > + > + dw_hdmi_remove(hdmi); > +} > + > +static const struct of_device_id th1520_dw_hdmi_of_table[] = { > + { .compatible = "thead,th1520-dw-hdmi" }, > + { /* Sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, th1520_dw_hdmi_of_table); > + > +static struct platform_driver th1520_dw_hdmi_platform_driver = { > + .probe = th1520_dw_hdmi_probe, > + .remove = th1520_dw_hdmi_remove, > + .driver = { > + .name = "th1520-dw-hdmi", > + .of_match_table = th1520_dw_hdmi_of_table, > + }, > +}; > + > +module_platform_driver(th1520_dw_hdmi_platform_driver); > + > +MODULE_AUTHOR("Icenowy Zheng "); > +MODULE_DESCRIPTION("T-Head TH1520 HDMI Encoder Driver"); > +MODULE_LICENSE("GPL"); -- -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstr. 146, 90461 Nürnberg, Germany, www.suse.com GF: Jochen Jaser, Andrew McDonald, Werner Knoblich, (HRB 36809, AG Nürnberg)