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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-615a8f15a66sm18447502a12.16.2025.08.11.01.40.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Aug 2025 01:40:09 -0700 (PDT) Message-ID: Date: Mon, 11 Aug 2025 10:40:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/17] drm/msm/a6xx: Fix PDC sleep sequence To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250720-ifpc-support-v1-0-9347aa5bcbd6@oss.qualcomm.com> <20250720-ifpc-support-v1-5-9347aa5bcbd6@oss.qualcomm.com> <937197e9-09dd-4f3c-bdb4-4001f5217c07@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: tuMcGalmkLCNAQlA8v0NG_oTep99ijGd X-Authority-Analysis: v=2.4 cv=RunFLDmK c=1 sm=1 tr=0 ts=6899ac6b cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=qoSIoJJoY18thYJL65kA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-GUID: tuMcGalmkLCNAQlA8v0NG_oTep99ijGd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA5MDAxOCBTYWx0ZWRfXx6ci3+Q89rLd NhJ9hzkfq27M60fzAE4R0qIRTKbKsvBYhiqRLBUkSKCIA3W1ml/6WfCFQrNvgdZRL8EYGgVZ8Ga puUB821YVq5oKjlndYyN4mUqdJCe38FTVkx9pl9Vo1RGlkc3KgqlT/OfctQeeq6enNRmsDMzxd4 wjWUhTUf2dJV9Hqpc6519DQEEzCLKNfJkGF+X/4a4eQzs+DsPFlT9jhAegdIFW/j6lGpB5hFcjO hzQ2qT9fVoZW4Ty63HhV8wJCMV3ah+SLM6CVpWLe0QmFskAWy0H98Mrg9ZFe16EqkyjfAA9Aanq Q50fw6YIX/2OdEYO5D6P6dbJu63JwrWti8wBv0W2Z9ReqrseHO4MxMAi+Je+Qf/Atl0DfpQ1S+V R/as+mEc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-11_01,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508090018 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 8/8/25 7:22 PM, Akhil P Oommen wrote: > On 8/7/2025 7:21 PM, Konrad Dybcio wrote: >> On 7/20/25 2:16 PM, Akhil P Oommen wrote: >>> Since the PDC resides out of the GPU subsystem and cannot be reset in >>> case it enters bad state, utmost care must be taken to trigger the PDC >>> wake/sleep routines in the correct order. >>> >>> The PDC wake sequence can be exercised only after a PDC sleep sequence. >>> Additionally, GMU firmware should initialize a few registers before the >>> KMD can trigger a PDC sleep sequence. So PDC sleep can't be done if the >>> GMU firmware has not initialized. Track these dependencies using a new >>> status variable and trigger PDC sleep/wake sequences appropriately. >>> >>> Signed-off-by: Akhil P Oommen >>> --- >> >> FWIW some time ago I made this patch, which tackles a similar issue, >> perhaps it's a good idea to merge both: >> >> From 7d6441fc6ec5ee7fe723e1ad86d11fdd17bee922 Mon Sep 17 00:00:00 2001 >> From: Konrad Dybcio >> Date: Thu, 20 Feb 2025 10:28:51 +0100 >> Subject: [PATCH] drm/msm/adreno: Delay the Adreno RPMh startup to HFI init >> >> There's no use in trying to power up the GX logic before we're almost >> ready to fire up the GPU. In fact, with A8xx the PDC and RSC uCode are >> loaded by the GMU firmware, so we *must* wait for the GMU to fully >> initialize before trying to do so. >> > > iirc, this wake up sequence should be done before fw start. That aligns > with downstream sequence order too. FWIW techpack/graphics adreno_gen7_gmu.c @ gfx-kernel.lnx.15.0.r3-rel adb0a9da173e ("kgsl: rgmu: corrected pm suspend flag check on resume") // load gmu fw, enable clocks, irq, set up chipid etc. [...] // unmask CM3_SYSRESET ret = gen7_gmu_device_start(adreno_dev); if (ret) goto err; if (!test_bit(GMU_PRIV_PDC_RSC_LOADED, &gmu->flags)) { // set PDC_GPU_ENABLE_PDC & seq_start_addr ret = gen7_load_pdc_ucode(adreno_dev); if (ret) goto err; // disable hwcg, sleep/wake handshake setup, pdc ucode gen7_load_rsc_ucode(adreno_dev); set_bit(GMU_PRIV_PDC_RSC_LOADED, &gmu->flags); } // set HFI_CTRL_INIT ret = gen7_gmu_hfi_start(adreno_dev); if (ret) goto err; // continue booting the gpus, send out feature messages on a830, the patch is observably necessary (gmu doesn't start otherwise) Konrad