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From: Nancy.Lin <nancy.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>, Rob Herring <robh+dt@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>, <wim@linux-watchdog.org>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>, <linux@roeck-us.net>
Cc: devicetree@vger.kernel.org, David Airlie <airlied@linux.ie>,
	"jason-jh . lin" <jason-jh.lin@mediatek.com>,
	singo.chang@mediatek.com, llvm@lists.linux.dev,
	Nick Desaulniers <ndesaulniers@google.com>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Project_Global_Chrome_Upstream_Group@mediatek.com,
	linux-mediatek@lists.infradead.org,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	Nathan Chancellor <nathan@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v19 08/25] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
Date: Wed, 4 May 2022 13:59:13 +0800	[thread overview]
Message-ID: <e13bb5e13741cf74bdddcb97d89973d002fa0f83.camel@mediatek.com> (raw)
In-Reply-To: <2ada19798841f09d1a5675a8e3fb56f56cb778c1.camel@mediatek.com>

Hi CK,

 * Thanks for the review.

On Wed, 2022-05-04 at 13:28 +0800, CK Hu wrote:
> Hi, Nancy:
> 
> On Tue, 2022-05-03 at 18:23 +0800, Nancy.Lin wrote:
> > Add cmdq support for mtk-mmsys config API.
> > The mmsys config register settings need to take effect with the
> > other
> > HW settings(like OVL_ADAPTOR...) at the same vblanking time.
> > 
> > If we use CPU to write the mmsys reg, we can't guarantee all the
> > settings can be written in the same vblanking time.
> > Cmdq is used for this purpose. We prepare all the related HW
> > settings
> > in one cmdq packet. The first command in the packet is "wait stream
> > done",
> > and then following with all the HW settings. After the cmdq packet
> > is
> > flush to GCE HW. The GCE waits for the "stream done event" to
> > coming
> > and then starts flushing all the HW settings. This can guarantee
> > all
> > the settings flush in the same vblanking.
> > 
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  drivers/soc/mediatek/mtk-mmsys.c       | 52 ++++++++++++++++++----
> > ----
> >  include/linux/soc/mediatek/mtk-mmsys.h | 15 ++++++--
> >  2 files changed, 48 insertions(+), 19 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 199503dd544a..cd92db3d36fa 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -177,6 +177,7 @@ struct mtk_mmsys {
> >  	spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> >  	struct reset_controller_dev rcdev;
> >  	phys_addr_t io_start;
> > +	struct cmdq_client_reg cmdq_base;
> >  };
> >  
> >  static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> > @@ -191,10 +192,20 @@ static int
> > mtk_mmsys_find_match_drvdata(struct
> > mtk_mmsys *mmsys,
> >  	return -EINVAL;
> >  }
> >  
> > -static void mtk_mmsys_write_reg(struct mtk_mmsys *mmsys, u32
> > offset,
> > u32 mask, u32 val)
> > +static void mtk_mmsys_write_reg(struct mtk_mmsys *mmsys, u32
> > offset,
> > u32 mask, u32 val,
> > +				struct cmdq_pkt *cmdq_pkt)
> >  {
> >  	u32 tmp;
> >  
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +	if (cmdq_pkt && mmsys->cmdq_base.size) {
> > +		cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> > +				    mmsys->cmdq_base.offset + offset,
> > val,
> > +				    mask);
> > +		return;
> > +	}
> > +#endif
> 
> How do we process the condition that cmdq_pkt != 0 and mmsys-
> > cmdq_base.size == 0? That means DRM driver want to use cmdq control
> 
> but mmsys does not support cmdq function. This maybe an error that
> mmsys device node lose gce property. So I would like to print error
> message in this case.
> 
> Regards,
> CK
> 

OK, I will add an error message in this case.

Regards,
Nancy
> > +
> >  	tmp = readl_relaxed(mmsys->regs + offset);
> >  	tmp = (tmp & ~mask) | val;
> >  	writel_relaxed(tmp, mmsys->regs + offset);
> > @@ -210,7 +221,8 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> >  
> >  	for (i = 0; i < mmsys->data->num_routes; i++)
> >  		if (cur == routes[i].from_comp && next ==
> > routes[i].to_comp)
> > -			mtk_mmsys_write_reg(mmsys, routes[i].addr,
> > routes[i].mask, routes[i].val);
> > +			mtk_mmsys_write_reg(mmsys, routes[i].addr,
> > routes[i].mask, routes[i].val,
> > +					    NULL);
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> >  
> > @@ -224,42 +236,46 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> >  
> >  	for (i = 0; i < mmsys->data->num_routes; i++)
> >  		if (cur == routes[i].from_comp && next ==
> > routes[i].to_comp)
> > -			mtk_mmsys_write_reg(mmsys, routes[i].addr,
> > routes[i].mask, 0);
> > +			mtk_mmsys_write_reg(mmsys, routes[i].addr,
> > routes[i].mask, 0, NULL);
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >  
> > -void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> > width, int height)
> > +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> > width, int height,
> > +				  struct cmdq_pkt *cmdq_pkt)
> >  {
> >  	mtk_mmsys_write_reg(dev_get_drvdata(dev),
> > MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
> > -			    ~0, height << 16 | width);
> > +			    ~0, height << 16 | width, cmdq_pkt);
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
> >  
> > -void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int
> > be_height)
> > +void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int
> > be_height,
> > +			   struct cmdq_pkt *cmdq_pkt)
> >  {
> >  	mtk_mmsys_write_reg(dev_get_drvdata(dev),
> > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
> > -			    be_height << 16 | be_width);
> > +			    be_height << 16 | be_width, cmdq_pkt);
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_confing);
> >  
> >  void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool
> > alpha_sel, u16 alpha,
> > -			       u8 mode, u32 biwidth)
> > +			       u8 mode, u32 biwidth, struct cmdq_pkt
> > *cmdq_pkt)
> >  {
> >  	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> >  
> >  	mtk_mmsys_write_reg(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx -
> > 1) * 4, ~0,
> > -			    alpha << 16 | alpha);
> > +			    alpha << 16 | alpha, cmdq_pkt);
> >  	mtk_mmsys_write_reg(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 +
> > idx),
> > -			    alpha_sel << (19 + idx));
> > +			    alpha_sel << (19 + idx), cmdq_pkt);
> >  	mtk_mmsys_write_reg(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx -
> > 1) * 4,
> > -			    GENMASK(31, 16) | GENMASK(1, 0), biwidth <<
> > 16 | mode);
> > +			    GENMASK(31, 16) | GENMASK(1, 0),
> > +			    biwidth << 16 | mode, cmdq_pkt);
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
> >  
> > -void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> > bool channel_swap)
> > +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> > bool channel_swap,
> > +				     struct cmdq_pkt *cmdq_pkt)
> >  {
> >  	mtk_mmsys_write_reg(dev_get_drvdata(dev),
> > MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
> > -			    BIT(4), channel_swap << 4);
> > +			    BIT(4), channel_swap << 4, cmdq_pkt);
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
> >  
> > @@ -272,9 +288,9 @@ static int mtk_mmsys_reset_update(struct
> > reset_controller_dev *rcdev, unsigned l
> >  	spin_lock_irqsave(&mmsys->lock, flags);
> >  
> >  	if (assert)
> > -		mtk_mmsys_write_reg(mmsys, mmsys->data-
> > >sw0_rst_offset, 
> > BIT(id), 0);
> > +		mtk_mmsys_write_reg(mmsys, mmsys->data-
> > >sw0_rst_offset, 
> > BIT(id), 0, NULL);
> >  	else
> > -		mtk_mmsys_write_reg(mmsys, mmsys->data-
> > >sw0_rst_offset, 
> > BIT(id), BIT(id));
> > +		mtk_mmsys_write_reg(mmsys, mmsys->data-
> > >sw0_rst_offset, 
> > BIT(id), BIT(id), NULL);
> >  
> >  	spin_unlock_irqrestore(&mmsys->lock, flags);
> >  
> > @@ -364,6 +380,12 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> >  		mmsys->data = match_data->drv_data[0];
> >  	}
> >  
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +	ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> > +	if (ret)
> > +		dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > +#endif
> > +
> >  	platform_set_drvdata(pdev, mmsys);
> >  
> >  	clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > > clk_driver,
> > 
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index fe620929b0f9..7a73305390ba 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -6,6 +6,10 @@
> >  #ifndef __MTK_MMSYS_H
> >  #define __MTK_MMSYS_H
> >  
> > +#include <linux/mailbox_controller.h>
> > +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> >  enum mtk_ddp_comp_id;
> >  struct device;
> >  
> > @@ -73,13 +77,16 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> >  			      enum mtk_ddp_comp_id cur,
> >  			      enum mtk_ddp_comp_id next);
> >  
> > -void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> > width, int height);
> > +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> > width,
> > +				  int height, struct cmdq_pkt
> > *cmdq_pkt);
> >  
> > -void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int
> > be_height);
> > +void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int
> > be_height,
> > +			   struct cmdq_pkt *cmdq_pkt);
> >  
> >  void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool
> > alpha_sel, u16 alpha,
> > -			       u8 mode, u32 biwidth);
> > +			       u8 mode, u32 biwidth, struct cmdq_pkt
> > *cmdq_pkt);
> >  
> > -void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> > bool channel_swap);
> > +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> > bool channel_swap,
> > +				     struct cmdq_pkt *cmdq_pkt);
> >  
> >  #endif /* __MTK_MMSYS_H */
> 
> 


  reply	other threads:[~2022-05-04  5:59 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03 10:23 [PATCH v19 00/25] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 01/25] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 02/25] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2022-05-04  3:50   ` Rex-BC Chen
2022-05-04  6:06     ` Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 03/25] dt-bindings: mediatek: add ethdr definition for mt8195 Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 04/25] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components Nancy.Lin
2022-05-03 12:19   ` AngeloGioacchino Del Regno
2022-05-04  3:39   ` CK Hu
2022-05-03 10:23 ` [PATCH v19 05/25] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2022-05-04  3:45   ` CK Hu
2022-05-03 10:23 ` [PATCH v19 06/25] soc: mediatek: add mtk_mmsys_write_reg API Nancy.Lin
2022-05-03 12:19   ` AngeloGioacchino Del Regno
2022-05-04  1:36     ` Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 07/25] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
2022-05-04  5:05   ` CK Hu
2022-05-03 10:23 ` [PATCH v19 08/25] soc: mediatek: add cmdq support of " Nancy.Lin
2022-05-04  5:28   ` CK Hu
2022-05-04  5:59     ` Nancy.Lin [this message]
2022-05-03 10:23 ` [PATCH v19 09/25] soc: mediatek: mmsys: add mmsys for support 64 reset bits Nancy.Lin
2022-05-03 12:19   ` AngeloGioacchino Del Regno
2022-05-04  5:34   ` CK Hu
2022-05-03 10:23 ` [PATCH v19 10/25] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 Nancy.Lin
2022-05-04  5:37   ` CK Hu
2022-05-03 10:23 ` [PATCH v19 11/25] soc: mediatek: add mtk-mutex component - dp_intf1 Nancy.Lin
2022-05-03 12:19   ` AngeloGioacchino Del Regno
2022-05-04  5:53   ` CK Hu
2022-05-03 10:23 ` [PATCH v19 12/25] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2022-05-04  5:55   ` CK Hu
2022-05-03 10:23 ` [PATCH v19 13/25] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 14/25] drm/mediatek: add display merge advance config API " Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 15/25] drm/mediatek: add display merge start/stop API for cmdq support Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 16/25] drm/mediatek: add display merge mute/unmute support for MT8195 Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 17/25] drm/mediatek: add display merge async reset control Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 18/25] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 19/25] drm/mediatek: add mediatek-drm plane color encoding info Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 20/25] drm/mediatek: add ovl_adaptor support for MT8195 Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 21/25] drm/mediatek: add dma dev get function Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 22/25] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 23/25] drm/mediatek: add drm ovl_adaptor sub driver for MT8195 Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 24/25] drm/mediatek: add mediatek-drm of vdosys1 support " Nancy.Lin
2022-05-03 10:23 ` [PATCH v19 25/25] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin

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