From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BBDB5C43219 for ; Tue, 8 Nov 2022 11:02:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 897E910E25F; Tue, 8 Nov 2022 11:02:22 +0000 (UTC) Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by gabe.freedesktop.org (Postfix) with ESMTPS id 64B1A10E269 for ; Tue, 8 Nov 2022 11:02:19 +0000 (UTC) Received: by mail-lj1-x22a.google.com with SMTP id z24so20534079ljn.4 for ; Tue, 08 Nov 2022 03:02:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=cn8xDfZvXsB41XkQwJ5O0ptc1Al1vldhnYatc7I/dps=; b=HjVF5flkezC2CUkVw2fV7PUN3JxWfls0uUR864b8ktY560GsUH/fp8ti2i1GLLXkUu YhNtFqzDqm2WGFB8iHUPUUkujF4RkVq8xWfOzoinJEipEprHeZM92gV2b57uGpI1uLTE HyG/FVI8cbTym6wbNsWWmMbj8L3CeQgdAEjQFx7Ez2NhPXCtB+mKWpZsecGD+h6sLteM b5YOTLYRoPO7pbDnT0dBRg0Fbav+FH8l7+ESgsJOtv1HafKmvNsLZlvMc7aqwRA/ek+o DMtEH99PkRW2rc9X6v1XWUl5mTZ5AfounvVcXKcbYe270j3Kk489+7WMPqtAJ9yqOs+q yVag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cn8xDfZvXsB41XkQwJ5O0ptc1Al1vldhnYatc7I/dps=; b=6X+AsbTLQ8S5ZXNE1rO/oFhYrtg12DCPo84CntjMcqOGtTm5yFUHBwmkYT7aHnbAli xczLj7ZuIl4/SNjNwOiF4RtTzluliq6q7fObVvJPe8ViOOur3fRthYJriYq9w6R9bTf8 W+jdb7suRWUAdYKUuOfbwUn+9RuwYTMwLxA0xffjfGx5MkVLgGlz6HFAVA46ObYvxrYr 4yaksfQS0HlYKpFlyIiTAbA6XurarJ04X2zeSl9KOSWzmtwNK4go0ISlzsCz6LwdomIQ fcZq2hYpf++Yt9MKeQnO6ctHcPiTd7IKT8PXurWI00dk7NOaUhOn39wojktzfVhLWfbg 8uFQ== X-Gm-Message-State: ACrzQf0vx8NCNY6t5IfNcYQLImov2Vqj9k637cGxsqQd72pnHGHyFNRl mAeXAR5WszhXz8JIaWqQtOzpCg== X-Google-Smtp-Source: AMsMyM6HCaaxxudPzb046JtNcBohEMFbaPXk3HJh9n9Nw2CpwimyduwKlvf0NuOGh3LYP+a4btI0jA== X-Received: by 2002:a2e:8919:0:b0:277:22ee:ca2b with SMTP id d25-20020a2e8919000000b0027722eeca2bmr18049090lji.465.1667905337655; Tue, 08 Nov 2022 03:02:17 -0800 (PST) Received: from [192.168.0.20] (088156142199.dynamic-2-waw-k-3-2-0.vectranet.pl. [88.156.142.199]) by smtp.gmail.com with ESMTPSA id bi27-20020a0565120e9b00b0049f9799d349sm1726558lfb.187.2022.11.08.03.02.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Nov 2022 03:02:17 -0800 (PST) Message-ID: Date: Tue, 8 Nov 2022 12:02:16 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v3 3/8] dt-bindings: display/msm: add support for the display on SM8450 Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski References: <20221104130324.1024242-1-dmitry.baryshkov@linaro.org> <20221104130324.1024242-4-dmitry.baryshkov@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20221104130324.1024242-4-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM8450 platform. > > Signed-off-by: Dmitry Baryshkov > --- > .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ > .../display/msm/qcom,sm8450-mdss.yaml | 347 ++++++++++++++++++ > 2 files changed, 479 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > new file mode 100644 > index 000000000000..090a6506c8e9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > @@ -0,0 +1,132 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8450 Display DPU > + > +maintainers: > + - Dmitry Baryshkov > + > +$ref: /schemas/display/msm/dpu-common.yaml# > + > +properties: > + compatible: > + const: qcom,sm8450-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display hf axi > + - description: Display sf axi > + - description: Display ahb > + - description: Display lut > + - description: Display core > + - description: Display vsync > + > + clock-names: > + items: > + - const: bus > + - const: nrt_bus > + - const: iface > + - const: lut > + - const: core > + - const: vsync > + > +unevaluatedProperties: false You should require here properties provided by this schema. Otherwise it is a bit trickier to get what is actually required. I'll comment on your dependency patchset as well. > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + display-controller@ae01000 { > + compatible = "qcom,sm8450-dpu"; > + reg = <0x0ae01000 0x8f000>, > + <0x0aeb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8450_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf2_out: endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-172000000{ > + opp-hz = /bits/ 64 <172000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-325000000 { > + opp-hz = /bits/ 64 <325000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > new file mode 100644 > index 000000000000..9b6e1e03dc78 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > @@ -0,0 +1,347 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8450 Display MDSS > + > +maintainers: > + - Dmitry Baryshkov > + > +description: > + SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like > + DPU display controller, DSI and DP interfaces etc. > + > +$ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + const: qcom,sm8450-mdss > + > + clocks: > + items: > + - description: Display AHB > + - description: Display hf AXI > + - description: Display sf AXI > + - description: Display core > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: nrt_bus > + - const: core > + > + iommus: > + maxItems: 1 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + maxItems: 2 > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,sm8450-dpu > + > + "^dsi@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,mdss-dsi-ctrl > + > + "^phy@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-phy-5nm-8450 > + > +unevaluatedProperties: false Ditto Best regards, Krzysztof